tag: Synopsys

Achieve 10X Faster CDC Debug Leveraging Machine Learning
By Synopsys - 25 Jan, 2023 - Comments: 0

Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations ... » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2023 - Comments: 0

Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2023 - Comments: 0

Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

EV Architectures Evolving For Communication, Connectivity
By Marie C. Baca - 18 Jan, 2023 - Comments: 0

Electric vehicle architectures are rapidly evolving to accommodate multiple forms of connectivity, including in-vehicle, vehicle-to-vehicle, and vehicle-to-infrastructure communication. But so far, automotive OEMs have yet to come to a consensus on the winning technologies or the necessary standards — all of which will be necessary as cars become increasingly autonomous and increasingly inter... » read more

Selecting The Right RISC-V Core
By Brian Bailey - 16 Jan, 2023 - Comments: 0

With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or in open-source form, end users face an increasingly difficult challenge of ensuring they make the best choices. Each user likely will have a set of needs and concerns that almost equals th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Jan, 2023 - Comments: 0

With funding from the Semiconductor Research Corporation, a group of 10 universities is banding together to create the Processing with Intelligent Storage and Memory center, or PRISM, led by University of California San Diego. The $50.5 million PRISM center will focus on four different themes: novel memory and storage devices and circuits; next generation architectures; systems and software; an... » read more

Design And Verification Methodologies Breaking Down
By Brian Bailey - 12 Jan, 2023 - Comments: 0

Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

Will Floating Point 8 Solve AI/ML Overhead?
By Karen Heyman - 12 Jan, 2023 - Comments: 2

While the media buzzes about the Turing Test-busting results of ChatGPT, engineers are focused on the hardware challenges of running large language models and other deep learning networks. High on the ML punch list is how to run models more efficiently using less power, especially in critical applications like self-driving vehicles where latency becomes a matter of life or death. AI already ... » read more

Growing System Complexity Drives More IP Reuse
By Ann Mutschler - 12 Jan, 2023 - Comments: 1

IP reuse of both third-party and internal IP is growing, but it's also becoming more complex to manage. There is more IP being used, and more systems into which it needs to be integrated, combined with other IP, and tracked throughout an organization. In some cases, this is an economic requirement. In others, designs are so complex that engineering teams need to focus on where they will make... » read more

What Designers Need To Know About USB Low-Power States
By Synopsys - 11 Jan, 2023 - Comments: 0

In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond t... » read more

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