tag: Synopsys

Blog Review: Sept. 21
By Jesse Allen - 21 Sep, 2022 - Comments: 0

Arm's Neil Burgess and Sangwon Ha explain why they've joined Intel and Nvidia in proposing a new 8-bit floating point specification to enable neural network models developed on one platform to be run on other platforms without encountering the overhead of having to convert the vast amounts of model data between formats while reducing task loss to a minimum. Synopsys' Manuel Mota examines ver... » read more

Securing The Aerospace And Defense Microelectronics Supply Chain With DoD Trusted Suppliers
By Brad Bailey - 19 Sep, 2022 - Comments: 0

Since our inception 35 years ago, Synopsys has supported the U.S. defense industry. Over the last five years, we’ve increased our efforts with the government and aerospace sectors via program support at Defense Advanced Research Projects Agency (DARPA) and Intelligence Advanced Research Projects Activity (IARPA) as well as at traditional and non-traditional defense prime contractors. In 20... » read more

The High Price Of Smaller Features
By Katherine Derbyshire - 15 Sep, 2022 - Comments: 0

The semiconductor industry’s push for higher numerical apertures is driven by the relationship between NA and critical dimension. As the NA goes up, the CD goes down: Where λ is the wavelength and k1 is a process coefficient. While 0.55 NA exposure systems will improve resolution, Larry Melvin, principal engineer at Synopsys, noted that smaller features always come with a process cos... » read more

Blog Review: Sept. 14
By Jesse Allen - 14 Sep, 2022 - Comments: 0

Synopsys' Godwin Maben, Piyush Sancheti, and Hany Elhak examine some of the top chip design considerations for medical devices and why they require careful analysis of power to reduce the number surgeries to replace batteries, reliability for devices that can be expected to last for ten years or more, and security to protect private medical data and prevent breaches. Siemens' Chris Spear exp... » read more

What Is UCIe?
By Manuel Mota - 13 Sep, 2022 - Comments: 0

The semiconductor industry is undertaking a major strategy shift towards multi-die systems. The shift is fueled by several converging trends: Size of monolithic SoCs is becoming too big for manufacturability Some SoC functionalities may require different process nodes for optimal implementation Desire for enhanced product scalability and composability is increasing Multi-die syste... » read more

Rethinking Machine Learning For Power
By Brian Bailey - 13 Sep, 2022 - Comments: 0

The power consumed by machine learning is exploding, and while advances are being made in reducing the power consumed by them, model sizes and training sets are increasing even faster. Even with the introduction of fabrication technology advances, specialized architectures, and the application of optimization techniques, the trend is disturbing. Couple that with the explosion in edge devices... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Sep, 2022 - Comments: 0

Revenue for the top 10 IC design houses globally hit US$ 39.6 billion in 2Q22, a 32% growth over the prior year, according to a Trendforce report. The firm contends this growth trend will be difficult to maintain due to the high preceding base period and overall worse market conditions. Renesas introduced a RISC-V MCU specifically optimized for advanced motor control systems. The new ASSP in... » read more

Test Data Streaming For The Next Generation Of Designs
By Rahul Singhal - 08 Sep, 2022 - Comments: 0

Semiconductor chips have been evolving to meet the demands of rapidly transforming applications, and so has the test technology to meet the test goals of those chips. Going back two decades or so, the applications were limited and the designs were simpler, thus the concerns about power, performance and area (PPA), turn-around time, re-use and time-to-market, etc., were important but not as crit... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs
By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

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