tag: test

Zero Trust Security In Chip Manufacturing
By Ed Sperling - 08 Feb, 2023 - Comments: 0

More equipment vendors and more IP are making the data in a fab much more valuable than in the past, and a potential target for hackers. What’s needed is a different approach to architecting and deploying services and equipment, so breaches can be stopped before they affect other equipment and data, and a better way of sharing data. Brian Buras, production analytics solution architect at Adva... » read more

Using Machine Learning To Automate Debug Of Simulation Regression Results
By Synopsys - 08 Feb, 2023 - Comments: 0

Regression failure debug is usually a manual process wherein verification engineers debug hundreds, if not thousands of failing tests. Machine learning (ML) technologies have enabled an automated debug process that not only accelerates debug but also eliminates errors introduced by manual efforts. This white paper discusses how verification engineers can more efficiently analyze, bin, triage... » read more

The 5G mmWave Commercialization Effort Is Underway
By David Vondran - 07 Feb, 2023 - Comments: 0

By David Vondran and Rodrigo Carrillo-Ramirez 5G broadband cellular technology entered its first major rollout phase in 2019. In recent years, 5G adoption has been very visible among the consumer electronics industry, with 5G capabilities now being a key selling point for mid-tier to high-end mobile devices. Behind the scenes, however, there have been a number of developments designed to ... » read more

Engineering Test Station Facilitates Post-Silicon Validation
By Adir Zonta - 07 Feb, 2023 - Comments: 0

The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example. These challenges arise f... » read more

Scan Pattern Portability From PSV To ATE To SLT To IST
By Ash Patel - 30 Jan, 2023 - Comments: 0

By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Looking Inside Of Chips
By Ed Sperling - 10 Jan, 2023 - Comments: 0

Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Emerging Technologies Are Driving System Level Test Adoption
By Natalian Z. Der - 10 Jan, 2023 - Comments: 0

With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test... » read more

Industrial Solutions For Machine-Learning-Enabled Yield Optimization And Test
By Sonny Banwari - 10 Jan, 2023 - Comments: 0

This article summarizes the content of a paper developed and presented by Advantest at ETS 2022. By Sonny Banwari and Matthias Sauer According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of ... » read more

Silent Data Corruption
By Ed Sperling - 12 Dec, 2022 - Comments: 0

Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Packetized Scan Test
By Siemens EDA - 06 Dec, 2022 - Comments: 0

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

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