tag: test

The Trouble With MEMS
By Ed Sperling - 25 May, 2016 - Comments: 0

The advent of the Internet of Things will open up a slew of new opportunities for MEMS-based sensors, but chipmakers are proceeding cautiously. There are a number of reasons for that restraint. Microelectromechanical systems are difficult to design, manufacture and test, which initially fueled optimism in the MEMS ecosystem that this market would command the same kinds of premiums that analo... » read more

Highly Parallel Wafer Level Reliability Systems With PXI SMUs
By NI - 18 May, 2016 - Comments: 1

Reliability testing has long served as a method of ensuring that semiconductor devices maintain their desired performance over a given lifetime. As IC manufacturers continue to introduce new and innovative processes with decreasing device geometries, they need to ensure the additional complexity from these changes does not affect the long-term reliability of their ICs. Additionally, major techn... » read more

Accelerating Design-For-Test Pattern Simulation
By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Automotive Semiconductor Test
By Mentor, a Siemens Business - 16 Mar, 2016 - Comments: 0

We are witnessing the gradual transition of the automobile from a simple means of transportation to a mobile electronic hub. The amount of electronic content in passenger cars continues to grow rapidly. Recent reports indicate that electronics now contribute about 40% of the total costs of a traditional, internal combustion engine car, and this jumps as high as 75% for the growing number of ele... » read more

What Goes Wrong With IP
By Ed Sperling - 10 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

6 Key Benefits Of Thermal Testing
By Mentor, a Siemens Business - 23 Nov, 2015 - Comments: 0

This whitepaper discusses the advantages of transient thermal test methods for IC package and thermal interface material (TIM) thermal characterization testing vs steady state methods. These methods assist verification of thermal performance for reliability, support package development & manufacturing decision making, and ensure accurate data sheet values used for selection by engineers. ... » read more

2.5D Creeps Into SoC Designs
By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

Lazy Or Bored: The Outcome Might Be The Same
By Tom De Schutter - 28 May, 2015 - Comments: 0

I recently talked to an engineering manager responsible for system validation at a major automotive company. The topic was the continuous growth of software content and how to reach the right software quality. He explained that for the part he is responsible for, most software is created by his suppliers. But because the carmaker is ultimately held responsible for any issue with the car, he has... » read more

Tech Talk: Power Tools
By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

EDT Test Points
By Mentor, a Siemens Business - 22 Jan, 2015 - Comments: 0

Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, cal... » read more

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