tag: test

Blog Review: April 30
By Ed Sperling - 30 Apr, 2014 - Comments: 0

Applied Materials’ Jeremy Read points to a looming problem for the Internet of Things—legacy fabs that will require software upgrades and advanced process control. Also needed: Sensors attached to thousands of machines for predictive maintenance. Foundries are now ready for production finFETs. Cadence's Richard Goering captures the buzz at last week’s TSMC Tech Symposium, where the ro... » read more

Executive Insight: CH Wu
By Ed Sperling - 21 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

DSP-Based Testing
By Various Writers - 16 Apr, 2014 - Comments: 0

ADC and DAC are the most typical mixed signal devices. In mixed signal testing, analog stimulus signal for an ADC is generated by an arbitrary waveform generator (AWG) which employs a D/A converter inside, and an analog signal out of a DAC is measured by a digitizer or a sampler which employs an A/D converter inside. The stimulus signals for these devices are created using mathematical method, ... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Enabling Test Portability With Graphs
By Ann Mutschler - 20 Mar, 2014 - Comments: 0

Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more

Test Challenges Rising For Mobile Devices
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Smartphone and tablets continue to advance at a dizzying pace. On the component side alone, the latest mobile devices are moving towards 64-bit application processors, multi-mode RF front-ends, higher-end cameras and flashy LCD screens. Some systems even boast fingerprint scanners and heart rate sensors. But an obvious part of the system continues to lag behind the curve—battery life. In r... » read more

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

SoC Integration Mistakes
By Ed Sperling - 26 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy