LLMs Show Promise In Secure IC Design


The introduction of large language models into the EDA flow could significantly reduce the time, effort, and cost of designing secure chips and systems, but they also could open the door to more sophisticated attacks. It's still early days for the use of LLMs in chip and system design. The technology is just beginning to be implemented, and there are numerous technical challenges that must b... » read more

Chip Industry Technical Paper Roundup: April 30


These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Chip Industry Technical Paper Roundup: April 23


New technical papers recently added to Semiconductor Engineering’s library. [table id=216 /] Find last week’s technical paper additions here. » read more

Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Memristor Crossbar Architecture for Encryption, Decryption and More


A new technical paper titled "Tunable stochastic memristors for energy-efficient encryption and computing" was published by researchers at Seoul National University, Sandia National Laboratories, Texas A&M University and Applied Materials. Abstract "Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirement... » read more

Hardware Fuzzer Utilizing LLMs


A new technical paper titled "Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing" was published by researchers at TU Darmstadt and Texas A&M University. Abstract "Modern computing systems heavily rely on hardware as the root of trust. However, their increasing complexity has given rise to security-critical vulnerabilities that cross-layer at-tacks can exploit. Traditional hardware ... » read more

Chip Industry Technical Paper Roundup: Mar. 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=201 /] » read more

Chip Industry Week In Review


By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

White-Box Fuzzer With Static Analysis To Detect And Locate Timing Vulnerabilities In RISC-V Processors 


A technical paper titled “WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors” was published by researchers at Indian Institute of Technology Madras, Texas A&M University, and Technische Universität Darmstadt. Abstract: "Timing vulnerabilities in processors have emerged as a potent threat. As processors are the foundation of any computing s... » read more

Chip Industry’s Technical Paper Roundup: Dec 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=174 /] More ReadingTechnical Paper Library home » read more

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