Designing In The Cloud

By Ranjit Adhikary - 06 Jun, 2019 - Comments: 0

Amazon AWS was launched back in 2006. Web based services such as Netflix and Expedia were early adopters, and AWS has grown rapidly, bringing in competition from Google (GCP), Microsoft (Azure) and others. It has taken a while for the design community to embrace the ‘cloud’ as some of the needs and concerns of design teams are different. Cloud vendors have recognized this untapped market ... » read more

Where Are We On The Road To Artificial Intelligence In Chip Design?

By Thomas Andersen - 25 Apr, 2019 - Comments: 0

It’s hard to find an article today that doesn’t talk about how Artificial Intelligence is going to solve every possible problem in the world. From self-driving cars, to robots running an entire hotel (in Japan), to voice assistants answering your every question, it appears that every problem can be solved with AI. As so often in life, the true answer is: it depends. It depends on the nature... » read more

DO-254 Solutions Blueprint

By Aldec - 19 Dec, 2018 - Comments: 0

The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL simulator, synthesis, place & route and static timing analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including requirements management, traceability, tests management, de... » read more

Can AI Alter The Burgeoning Design Cost Trend?

By Rich Wawrzyniak - 21 Jun, 2018 - Comments: 0

Everyone in the semiconductor design arena has experienced or at least observed the impact of increasing costs for complex SoC silicon. Semico’s recently released report entitled "Silicon and Software Design Cost Analysis" reveals the cost associated with a first time design effort for a high-end, advanced performance multicore SoC using 7nm process technology can top $195M for both the silic... » read more

Design Automation For Silicon Photonics: Pushing Research Into Production

By Chris Cone - 07 Jun, 2018 - Comments: 0

Silicon photonics is a transformative technology that will have a major impact on system architectures in future IC design applications. Already a major solution for Datacom applications and emerging applications in sensing, design techniques in silicon photonics, with the ability to leverage CMOS technology to integrate large numbers of photonic components, are now being applied to enable opti... » read more

Introduction To eFPGA Software

By Geoff Tate - 05 Apr, 2018 - Comments: 0

In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software. An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC. The clock(s) for the eFPGA come from the SoC. The configuration of the eFPGA is done by the SoC... » read more

Plugging Gaps In Advanced Packaging

By Ann Mutschler - 27 Sep, 2017 - Comments: 0

The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea... » read more

How To Buy Used Fab Tools

By Mark LaPedus - 18 Sep, 2014 - Comments: 0

Buying used equipment is a good way to find viable tools at reasonable prices. But the used equipment market is not a simple place to shop for good deals. As reported in this article, it’s a complex market. For example, buyers of fab tools can procure used gear from several sources—an OEM; a used equipment company; a broker; and through eBay. Some IDMs also sell used equipment. So what a... » read more

Making A Multicore System Work

By Ed Sperling - 29 Jan, 2009 - Comments: 0

If you think designing a single-core system is hard, designing multicore systems is multiple times harder. Connecting all the pieces together and making them work properly, if not together, is one of the hardest tasks design engineers and architects will ever face. System-Level Design tracked down some of the experts in this field and sat them down around a table to discuss what’s going... » read more

Houston…We Have A System-Level Problem

By Ed Sperling - 04 Dec, 2008 - Comments: 0

[youtube vid=iZ61OU12TNU] Just imagine what happens when the guidance system on the International Space Station goes on the fritz and the entire lab begins doing somersaults through outer space. Then the solar panels no longer work and the communication system fails, and suddenly you understand how serious system-level design problems can become. Ret. Capt. Daniel Bursch recounts the inciden... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?