tag: triple patterning

Litho Challenges Break The Design-Process Wall
By Katherine Derbyshire - 22 Jun, 2015 - Comments: 3

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process. Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancemen... » read more

One-On-One: Thomas Caulfield
By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Are Three Eyes Better Than Two?
By David Abercrombie - 16 Apr, 2015 - Comments: 0

It is clear that having two eyes is better than having just one. Not only is depth perception much better, but we get to enjoy 3D movies because of it. There is also some sense of security in knowing that if something terrible happened to one eye, you always have a backup. Have you ever wondered if these sorts of advantages are extendable? You’ve probably heard the phrase about someone ha... » read more

The Trouble With Triples—Part 2
By David Abercrombie - 23 Jan, 2014 - Comments: 1

In my last blog, we started to look at some of the challenges of triple patterning (TP) compared to double patterning (DP). In particular, we looked at the algorithmic complexity of determining if a valid coloring solution exists, and if so, producing a three-mask decomposition. This time, let’s look into the challenges of what to do if a layout is not legally decomposable into three colors. ... » read more

Blog Review: Nov. 20
By Ed Sperling - 20 Nov, 2013 - Comments: 0

Can you really heat your home office with just four candles? It all depends on where you put those candles, as Mentor’s Robin Bornoff shows in part one of this series. And make sure you check out the video, particularly if you’ve had a tough day. Synopsys’ Karen Bartleson interviews ST’s Oleg Logvinov on camera about the IoT, which may be the biggest change since the Industrial Revol... » read more

The Trouble With Triples—Part 1
By David Abercrombie - 14 Nov, 2013 - Comments: 0

If you’re a true geek like me, you may remember the Star Trek episode “The Trouble with Tribbles,” about the cute furry little aliens that purr when you pet them. They seemed so nice and friendly on the surface, but in the end, they became an exponentially growing mass of ravenous monsters that almost broke down the ship and consumed the storehouse of grain that was meant to provide human... » read more

You Ain’t Seen Nothing Yet
By David Abercrombie - 19 Sep, 2013 - Comments: 1

I’ve been talking about double patterning for a long time now in this series of blogs. I thought it might be good to start looking ahead at what is next for multi-patterning (Don’t Panic!). As you may have been hearing or reading, it doesn’t look like EUV lithography is going to be ready for 10nm, and may not even make it for 7nm. This means that alternative methods of extending the exist... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

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