tag: TSMC

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Sep, 2019 - Comments: 0

Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 27 Sep, 2019 - Comments: 0

Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Stacking Memory On Logic, Take Two
By Ed Sperling - 19 Sep, 2019 - Comments: 1

True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

Mixed Picture Seen For EUV Masks
By Mark LaPedus - 16 Sep, 2019 - Comments: 0

The confidence level of extreme ultraviolet (EUV) lithography continues to grow as the technology moves into production, but the EUV mask infrastructure remains a mixed picture, according to new surveys released by the eBeam Initiative. The EUV mask infrastructure involves several technologies that are in various stages of development. On one front, the outlook for several mask tool technol... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Sep, 2019 - Comments: 0

China's DRAM efforts Two memory vendors from China, Tsinghua Unigroup and ChangXin Memory Technology, have disclosed more details about their respective efforts to enter the DRAM arena. As reported, Tsinghua Unigroup wants to enter the DRAM business. Now, the China-based firm has secured land to build a new DRAM fab. The firm recently signed an agreement with the Chongqing government to e... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 30 Aug, 2019 - Comments: 0

Chipmakers GlobalFoundries has filed suits in the U.S. and Germany, alleging that semiconductor manufacturing technologies used by TSMC infringe upon 16 of GF's patents. The suits were filed in the U.S. International Trade Commission (ITC), the U.S. Federal District Courts in the Districts of Delaware and the Western District of Texas, and the Regional Courts of Dusseldorf and Mannheim in Germ... » read more

Advanced Packaging Options Increase
By Ed Sperling - 19 Aug, 2019 - Comments: 0

Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high performance is one of the main criteria. At least part of the problem is there is a spectrum of choices, which makes it hard to achieve economies of scale. Even where there is momentum for a particular ... » read more

Outlook For Masks, Materials and Wafers
By Mark LaPedus - 15 Aug, 2019 - Comments: 0

After a slowdown in the first half of 2019, chipmakers and equipment vendors face a cloudy outlook for the second half of this year, with a possible recovery in 2020. But what about other key technologies like materials, photomasks and silicon wafers? These are also critical for the semiconductor supply chain and are key indicators where the market is heading. In the first half of 2019, m... » read more

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