Toward High-End Fan-Outs

By Ed Sperling - 05 Mar, 2018 - Comments: 1

Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs

By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

FD-SOI Adoption Expands

By Ed Sperling - 21 Feb, 2018 - Comments: 2

Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

The Race To Accelerate

By Ed Sperling - 12 Feb, 2018 - Comments: 1

Geoff Tate, CEO of [getentity id="22921" e_name="Flex Logix"], sat down with Semiconductor Engineering to discuss how the chip industry is changing, why that bodes well for embedded FPGAs, and what you need to be aware of when using programmable logic on the same die as other devices. What follows are excerpts of that conversation. SE: What are the biggest challenges facing the chip industry... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 09 Feb, 2018 - Comments: 0

Chipmakers China has struck again, as the nation continues to acquire semiconductor technology. In December, Silicon Labs announced plans to acquire Sigma Designs for $282 million. The deal involves Sigma’s Z-Wave chip business. Now, Sigma Designs has sold its connectivity chip business unit to Integrated Silicon Solution Inc. (ISSI). In 2015, a Chinese consortium of investors led by Uph... » read more

Fan-Out Wars Begin

By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Cheaper Packaging Options Ahead

By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Dawn Of The Data-Centric Era

By Lara Chamness - 31 Jan, 2018 - Comments: 0

A recurring theme of the recent Industry Strategy Symposium (ISS) in Half Moon Bay, California, was how the explosion of new applications such as autonomous vehicles, digital healthcare, quantum computing, and crytocurrency mining are driving the need for more industry-wide collaboration to enable companies to compete in the “Data Centric” era. The resulting digital economy is creating unpr... » read more

Blog Review: Jan. 31

By Jesse Allen - 31 Jan, 2018 - Comments: 0

Cadence's Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work. In a video, Mentor's Colin Walls considers how to make the simplest possible multitasking scheduler with a one line RTOS. Synopsys' Sandeep Taneja checks out the technology behind airbags in cars and the role of the Motorola Serial Peripheral Interfac... » read more

Manufacturing Bits: Jan. 30

By Mark LaPedus - 30 Jan, 2018 - Comments: 0

SRC’s new R&D centers The Semiconductor Research Corp. has launched a network of research centers within its recently-announced Joint University Microelectronics Program (JUMP). SRC officially launched the 5-year, $200 million program on Jan. 1. With various research centers, the mission of JUMP is to lay the groundwork that extends the viability of Moore’s Law through 2040. The idea is... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

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