tag: University of Florida

Technical Paper Round-Up: March 29
By Linda Christensen - 29 Mar, 2022 - Comments: 0

Improving batteries, ultra low-power photonic edge computing, SLAM, Tellurium for 2D semiconductors, and reservoir computing top the past week's technical papers. The focus on energy is critical as the edge buildout continues and more devices are connected to a battery, while research into new architectures and materials that will continue scaling and improve performance per watt continue at th... » read more

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions
By Technical Paper Link - 28 Mar, 2022 - Comments: 0

Abstract "The ever-increasing usage and application of system-on-chips (SoCs) has resulted in the tremendous modernization of these architectures. For a modern SoC design, with the inclusion of numerous complex and heterogeneous intellectual properties (IPs),and its privacy-preserving declaration, there exists a wide variety of highly sensitive assets. These assets must be protected from any u... » read more

Technical Paper Round-Up: March 15
By Linda Christensen - 15 Mar, 2022 - Comments: 0

Research is expanding across a variety of semiconductor-related topics, from security to flexible substrates and chiplets. Unlike in the past, when work was confined to some of the largest universities, that research work is now being spread across a much broader spectrum of schools on a global basic, including joint research involving schools whose names rarely appeared together. Among the ... » read more

Quantifying Rowhammer Vulnerability for DRAM Security
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract: "Rowhammer is a memory-based attack that leverages capacitive-coupling to induce faults in modern dynamic random-access memory (DRAM). Over the last decade, a significant number of Rowhammer attacks have been presented to reveal that it is a severe security issue capable of causing privilege escalations, launching distributed denial-of-service (DDoS) attacks, and even runtime attack ... » read more

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Advances in Logic Locking: Past, Present, and Prospects
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs). Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses have been established across the globe over the past three decades. The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called wat... » read more

Quantifiable Assurance: From IPs to Platforms
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract: "Hardware vulnerabilities are generally considered more difficult to fix than software ones because of their persistent nature after fabrication. Thus, it is crucial to assess the security and fix the potential vulnerabilities in the earlier design phases, such as Register Transfer Level (RTL), gate-level or physical layout. The focus of the existing security assessment techniques i... » read more

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "FPGA bitstream encryption and authentication can be defeated by various techniques and it is critical to understand how these vulnerabilities enable extraction and tampering of commercial FPGA bitstreams. We exploit the physical vulnerability of bitstream encryption keys to readout using failure analysis equipment and conduct an end-to-end bitstream tamper attack. Our work undersco... » read more

Design of strongly nonlinear graphene nanoelectromechanical systems in quantum regime
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

ABSTRACT "We report on the analysis and design of atomically thin graphene resonant nanoelectromechanical systems (NEMS) that can be engineered to exhibit anharmonicity in the quantum regime. Analysis of graphene two-dimensional (2D) NEMS resonators suggests that with device lateral size scaled down to ∼10–30 nm, restoring force due to the third-order (Duffing) stiffness in graphene NE... » read more

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