tag: University of Florida

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Advances in Logic Locking: Past, Present, and Prospects
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs). Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses have been established across the globe over the past three decades. The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called wat... » read more

Quantifiable Assurance: From IPs to Platforms
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract: "Hardware vulnerabilities are generally considered more difficult to fix than software ones because of their persistent nature after fabrication. Thus, it is crucial to assess the security and fix the potential vulnerabilities in the earlier design phases, such as Register Transfer Level (RTL), gate-level or physical layout. The focus of the existing security assessment techniques i... » read more

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "FPGA bitstream encryption and authentication can be defeated by various techniques and it is critical to understand how these vulnerabilities enable extraction and tampering of commercial FPGA bitstreams. We exploit the physical vulnerability of bitstream encryption keys to readout using failure analysis equipment and conduct an end-to-end bitstream tamper attack. Our work undersco... » read more

Design of strongly nonlinear graphene nanoelectromechanical systems in quantum regime
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

ABSTRACT "We report on the analysis and design of atomically thin graphene resonant nanoelectromechanical systems (NEMS) that can be engineered to exhibit anharmonicity in the quantum regime. Analysis of graphene two-dimensional (2D) NEMS resonators suggests that with device lateral size scaled down to ∼10–30 nm, restoring force due to the third-order (Duffing) stiffness in graphene NE... » read more

Is There a Practical Test For Rowhammer Vulnerability?
By Bryon Moyer - 08 Jun, 2021 - Comments: 3

Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes
By Technical Paper Link - 31 Dec, 2020 - Comments: 0

Abstract: "Logic locking has been proposed as an obfuscation technique to protect outsourced IC designs from IP piracy by untrusted entities in the design and fabrication process. In this case, the netlist is locked by adding extra key-gates, and will be unlocked only if a correct key is applied to the key-gates. The key is assumed to be written into a non-volatile memory after the fabricati... » read more

Why It’s So Hard To Stop Cyber Attacks On ICs
By Ed Sperling - 23 Dec, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 26 Jun, 2020 - Comments: 0

Security The U.S. Defense Advanced Research Projects Agency (DARPA) selected Synopsys as the main contractor to provide SoC design tools and security IP for its Automatic Implementation of Secure Silicon (AISS) program. The four-year program’s goal to develop a design tool and IP ecosystem to automate adding security into integrated circuits. Synopsys will be working on a research team with ... » read more

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