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Technical Paper Round-up: April 26

Interleaved transistors; neuromorphic photonic modeling; re-using verification for security; 3D-IC reliability; memory bandwidth regulation.

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Find all technical papers in Semiconductor Engineering’s library.

Technical Paper Research Organizations
Efficacy Of Transistor Interleaving In DICE Flip-Flops At A 22 Nm FD SOI Technology Node University of Saskatchewan
Neuromorphic Photonic Circuit Modeling In Verilog-A Queen’s University, University of British Columbia, Princeton University
Reusing Verification Assertions As Security Checkers For Hardware Trojan Detection Centre for Hardware Security
Tallinn University of Technology (TalTech), Estonia
Artificial Intelligence Deep Learning For 3D IC Reliability Prediction National Yang Ming Chiao Tung University, National Center for High-Performance Computing (Taiwan), Tunghai University, MA-Tek Inc, and UCLA
Real-Time Instruction-Level Verification Of Remote IoT/CPS Devices Via Side Channels University of Florida
Tile-Based Massively Scalable MIMO And Phased Arrays For 5G/B5G-Enabled Smart Skins And Reconfigurable Intelligent Surfaces Georgia Tech
A Novel Power-Saving Reversing Camera System With Artificial Intelligence Object Detection National Yang Ming Chiao Tung University, Avisonic Technology Corp
Memory Bandwidth Regulation On Hybrid NVM/DRAM Platforms Shanghai Jiao Tong University
FLODAM: Cross-Layer Reliability Analysis Flow For Complex Hardware Designs Univ. Rennes, IRISA, ONERA, DGA, Temento
Van Der Waals Semiconductor Empowered Vertical Color Sensor Georgia State, Clemson University, Oak Ridge National Lab (ORNL)
Stress Tensor Mesostructures For Deterministic Figuring Of Thin Substrates MIT and University of Arizona, funded by NASA
Hardware-Supported Patching Of Security Bugs In Hardware IP Blocks Duke University, University of Calgary, NYU & Intel

 

Semiconductor Engineering is in the process of building this library of research papers.  Please send suggestions for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers.



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