tag: UPF

Mentor, Cadence Join Forces
By Ed Sperling - 15 Jun, 2015 - Comments: 0

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

Formal Low-Power Verification Of Power-Aware Designs
By Cadence - 15 Jun, 2015 - Comments: 0

Power reduction and management methods are now all pervasive in system- on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design th... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 18 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

UPF-Driven RTL Power Budgeting For Energy-Efficient Designs
By Arti Dwivedi - 09 Apr, 2015 - Comments: 1

Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology. While power management is critical in all design stages, an important aspect of this methodolog... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

An Update On The IEEE 1801-2013 Unified Power Format Standard
By Barry Pangrle - 09 Feb, 2015 - Comments: 0

It’s been almost six years since the first IEEE 1801 standard was officially published in March of 2009, but the standard can trace its roots back to years before that date. On May 30, 2013 the IEEE released a press announcement for the most recent version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). This brought forward a standard for the industry that is finally backed by all of the ma... » read more

Tech Talk: Set-Top Power
By Ed Sperling - 19 Jan, 2015 - Comments: 0

Broadcom's John Redmond, associate technical director for digital video technology, talks with Semiconductor Engineering about what the next-generation set-top boxes will look like and how they will save power. The video was shot at Cadence's Low Power Summit. [youtube vid=Ov2GFrUTzts] » read more

Unraveling Power Methodologies
By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

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