tag: UVM

Data-Driven Verification Begins
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis
By Mentor, a Siemens Business - 14 Mar, 2019 - Comments: 0

Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to clos... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

How to Connect Questa VIP to the Processor Verification Flow
By Codasip - 27 Feb, 2019 - Comments: 0

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Nov, 2018 - Comments: 0

Tools & Standards Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout... » read more

Make-Or-Break Time For Portable Stimulus
By Neil Johnson - 25 Oct, 2018 - Comments: 2

I’m pretty upbeat when it comes to portable stimulus. Or maybe it’d be better to say I’m pretty upbeat on the idea of portable stimulus. While doing my best to brush aside the usual EDA propaganda (propaganda I’ve found to be a bit haphazard, but more on that in a minute), I’ve put a lot of thought into how portable stimulus could fit into verification flows, the purpose of using it a... » read more

Is Software Necessary?
By Brian Bailey - 27 Aug, 2018 - Comments: 0

Hardware must be capable of running any software. While that might have been a good mantra when chips were relatively simple, it becomes an impossible verification task when dealing with SoCs that contain dozens of deeply embedded processors. When does it become necessary to use production software and what problems can that get you into? When verification targets such as power are added, it... » read more

Accessing Registers With UVM-RAL
By Sunil Sahoo - 23 Aug, 2018 - Comments: 0

As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it and each field can represent a particular feature that can be configured. The device then reads that register and uses that information to change settings or modes... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy