tag: validation

AV Testing Advances Without Standards
By Kevin Fogarty - 08 Jan, 2019 - Comments: 0

The failure of the AV START Act in the United States Senate did more than just delay U.S. federal regulations for self-driving car technology that has yet to progress beyond the pilot-test stage. It delayed discussions that could have narrowed the almost infinite number of choices automated vehicles (AVs) must be prepared to make by creating guidelines defining what constitutes "safe" operat... » read more

What Is SOTIF?
By Ed Sperling - 10 Oct, 2018 - Comments: 0

Arteris IP’s Kurt Shuler discusses new system-level best-practices approach to automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles. https://youtu.be/nC3TkF7c0Oo » read more

Fast-Tracking Safe Autonomous Vehicles
By Ansys - 16 May, 2018 - Comments: 0

You can't put a car on the road, a drone in the air or a robot in a warehouse without satisfying the strictest of safety standards. For an autonomous car, for example, this means driving billions of miles — a practical impossibility when time to market is critical. With ANSYS' complete solution for autonomous vehicles, you can put your machine through the required paces in a fraction of the t... » read more

Blog Review: May 9
By Jesse Allen - 09 May, 2018 - Comments: 0

Mentor's Doug Amos explains the differences (and similarities) between verification and validation, why switching between engines needs to be simpler, and why the limits of verification are driving a growth in validation importance. Synopsys' Melissa Kirschner provides a primer on 5G and the five technologies that will need to work in tandem to bring the promised high speeds and low latency.... » read more

Engineering Challenges for Viable Autonomous Vehicles
By Mentor, a Siemens Business - 02 May, 2018 - Comments: 0

The rise of autonomous and electric vehicles brings with it a host of engineering implications, including an increase in the number and variety of sensors in the vehicle, increasing software and hardware complexity, massive validation and verification cycles, heightened safety and security requirements, and new demands for digital data continuity. This paper is an overview of how six interdisci... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification
By James Paris - 26 Apr, 2018 - Comments: 0

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

Verification And Validation Brothers
By Brian Bailey - 22 Mar, 2018 - Comments: 0

At DVCon this year, Doug Amos took the stage for the [getentity id="22017" e_name="Mentor, a Siemens Business"] sponsored lunch presentation. For those of you who were there but decided to skip the lunch, expecting the traditional forced sales pitch, you made a mistake. Amos is one of those rare people who know how to inject humor, teaching and marketing into a single presentation such that the... » read more

Merging Verification With Validation
By Brian Bailey - 22 Mar, 2018 - Comments: 3

Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs
By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Co-modeling: A Powerful Capability For Hardware Emulation
By Mentor, a Siemens Business - 13 Dec, 2017 - Comments: 0

Understanding co-modeling technology, its impact on verification and validation should be a critical aim for anyone selecting and deploying emulation co-modeling resources. This paper explores how emulation co-modeling — specifically for the Veloce Strato emulation platform from Mentor, a Siemens business — is architected to meet the needs of advanced verification and validation. To rea... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy