Dealing With Noise In Image Sensors

By Karen Heyman - 01 Feb, 2024 - Comments: 0

The expanding use and importance of image sensors in safety-critical applications such as automotive and medical devices has transformed noise from an annoyance into a life-threatening problem that requires a real-time solution. In consumer cameras, noise typically results in grainy images, often associated with poor lighting, the speed at which an image is captured, or a faulty sensor. Typi... » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)

By Technical Paper Link - 27 Oct, 2023 - Comments: 0

A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs

By Technical Paper Link - 19 May, 2023 - Comments: 0

A new technical paper titled "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing" was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich, with funding by the German Research Foundation. Abstract "In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Deplet... » read more

Wafer-Scale Variability In Photonic Devices & Effects On Circuits

By Technical Paper Link - 25 Nov, 2022 - Comments: 0

A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

Next-Gen Transistors

By Ed Sperling - 07 Mar, 2022 - Comments: 0

Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

Design Technology Co-Optimization

By Ed Sperling - 18 Jan, 2022 - Comments: 0

Rising complexity is making it increasingly difficult to optimize chips for yield and reliability. David Fried, vice president of computational products at Lam Research, examines the benefits of automated rules to manage the relationship between layout and design requirements on one side, and process flows and rules/checks on the other. Benefits include reduced margin, shortened time to market,... » read more

Improving Robustness And Minimizing Over-Pessimism In The Face of Rising Design Variability

By Rahul Deokar - 14 Sep, 2021 - Comments: 0

Part 1 of this blog explored the problems facing designers working on Systems-on-a-Chip (SoCs) targeting energy-efficient design, and how Synopsys’ PrimeShield design robustness solution can help optimize designs for lower power while achieving aggressive time-to-market goals. This last part will delve into how the PrimeShield design robustness solution can help SoC designers optimize thei... » read more

Ins And Outs Of In-Circuit Monitoring

By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

Avoiding Gloom With Better Knowledge

By Stephen Crosher - 12 Mar, 2020 - Comments: 0

The rate of product development is facing very real challenges as the pace of silicon technology evolution begins to slow. Today, we are squeezing the most out of transistor physics, which is essentially derived from 60-year-old CMOS technology. To maintain the pace of Moore’s law, it is predicted that in 2030 we will need transistors to be a sixth of their current size. Reducing transistor s... » read more

Process Control For Next-Generation Memories

By Niranjan Khasgiwale - 18 Jul, 2019 - Comments: 0

The Internet of Things (IoT), Big Data and Artificial Intelligence (AI) are driving the need for higher speeds and more power-efficient computing. The industry is responding by bringing new memory technologies to the marketplace. Three new types of memory in particular—MRAM (magnetic random access memory), PCRAM (phase change RAM) and ReRAM (resistive RAM)—are emerging as leading candidat... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?