tag: verification

High Level Synthesis: Significant Differences Remain
By Brian Bailey - 09 Apr, 2014 - Comments: 1

In part 1 of this experts series on high-level synthesis (HLS), Semiconductor Engineering sat down with Mike Meredith, vice president of technical marketing at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. The initial part of the discussion looke... » read more

The Week In Review: Design
By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Big Shift In SoC Verification
By Ed Sperling - 31 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Get Ready For DVCon Europe
By Accellera - 28 Mar, 2014 - Comments: 0

By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

Enabling Test Portability With Graphs
By Ann Mutschler - 20 Mar, 2014 - Comments: 0

Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more

The Week In Review: Design
By Ed Sperling - 14 Mar, 2014 - Comments: 0

Tools Synopsys uncorked the next version of its verification tool, which includes static and formal verification, new debug capabilities, and low-power and X-propagation simulation. The company says the new tool offers up to 5X performance improvement. Cadence rolled out a new version of its verification solution for designs using ARM’s interconnect IP, speeding up verification and analys... » read more

Pointing Fingers In Verification
By Brian Bailey - 12 Mar, 2014 - Comments: 11

With most EDA tools, the buying decision is related to improved quality of results or increased productivity. Will a new synthesis or clock optimization tool enable designers to do more, faster and are those gains worth the price? The equation is fairly simple. When it comes to verification tools, things are more complex. You can still make productivity gains, or purchase an additional tool ... » read more

Big Shift In SoC Verification
By Ed Sperling - 06 Mar, 2014 - Comments: 5

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

The Week In Review: Design
By Ed Sperling - 28 Feb, 2014 - Comments: 0

Tools Cadence rolled out a new verification planning and management tool that is based on SQL, which greatly improves functionality and performance and offers multi-user, multi-engine and multi-analysis capabilities. Database technology—in this case, Structured Query Language—remains one of the very few software platforms that can harness multiple processors effectively. Synopsys unveil... » read more

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