tag: verification

A Fireside Chat With Imagination On Hardware-Assisted Development And Emulation
By Frank Schirrmeister - 13 May, 2015 - Comments: 0

During one of my trips to Europe I was able to sit down with Colin McKellar, senior director of hardware engineering at Imagination Technologies. He is my main contact for all things verification at Imagination. Imagination’s product challenges include maintaining the level of quality of their IP products within shorter timelines and dealing with integration of their IP into more complex c... » read more

Tech Talk: Faster SPICE
By Ed Sperling - 04 May, 2015 - Comments: 0

ProPlus CTO Bruce McGaughy explains why FastSPICE (fast Simulation Program with Integrated Circuit Emphasis) is running out of steam in the finFET generation and what needs to happen next. [youtube vid=07XzUQxPUr8] » read more

What Not To Verify
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

It is well understood that [getkc id="10" kc_name="verification"] is all about mitigating and managing risk, and success here begins with a good verification planning process. During the planning process, the project team creates a list of specific design functions and use cases that must be verified—and they identify the technique used to verify each specific item on the list. That list c... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Tech Talk: Virtual Prototyping
By Brian Bailey - 22 Apr, 2015 - Comments: 0

Bill Neifert, CTO of Carbon Design Systems, talks with about the intersection of IP and EDA, driven in particular by ARM's new architecture. [youtube vid=1OopYWmRarE] » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

First Time Success and Cost Control
By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Blog Review: March 18
By Jesse Allen - 18 Mar, 2015 - Comments: 0

How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

One-To-Many: Shifting Left, Adding Gears
By Brian Bailey - 12 Mar, 2015 - Comments: 3

[getperson id="11034" comment="Aart de Geus"], chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], launched into high gear for his keynote talk at this year’s Design and Verification Conference (DVCon). The gathering attracted a record number of attendees, and it is estimated that about 350 people crammed into the room to listen to him talk about the shift left that is happening ... » read more

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