tag: verification

What Will 2015 Bring For System-On-Chip Verification?
By Frank Schirrmeister - 29 Jan, 2015 - Comments: 0

Starting a new year, I always look back at predictions from years past to see how far off they were from reality and try to understand why. Rolling back 10 years, IEEE Spectrum published its annual “Winners and Losers” issue. Looking back, three predictions stick out for me. The first one is about how we consume media. Back in the January 2005 issue of IEEE Spectrum, Internet Protocol T... » read more

Speeding Up Timing Constraint Creation, Refinement And Validation
By Divya Macharla - 29 Jan, 2015 - Comments: 0

We are dealing with designs integrating many features and working with cutting-edge process technologies. Design methodologies and the design and process complexities can be overwhelming. To leverage the advancements in EDA tools and to achieve optimal power, performance and area results while overcoming design complexities, it is important to have a qualitative timing constraint file that c... » read more

Blog Review: Jan. 28
By Ed Sperling - 28 Jan, 2015 - Comments: 0

Mentor Graphics' John Day points to the growing presence of automakers in Silicon Valley. The latest émigré is Ford, which is setting up a research and innovation center in Palo Alto, but the company is hardly alone. Electronics could well become the real differentiators in vehicles. ARM's Andrew Sloss points to an intriguing relationship between data and economic growth—not to mention m... » read more

Unraveling Power Methodologies
By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

IP Design Essentials For Reliability And SoC Integration
By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

Is Your IP-Verification Environment Trying To Kill You?
By Larry Vivolo - 15 Jan, 2015 - Comments: 0

I was watching an old episode of The Office the other night. It was the one where a GPS guided the lead characters into a lake. While we've all fallen victim to a GPS gone bad. Most of us are fortunate enough not to trust technology blindly enough to drive into a lake (or in my case, onto the tarmac at Ft. Lauderdale International). Yet, it's surprisingly easy to find parallels in real life whe... » read more

Blog Review: Jan. 7
By Ed Sperling - 07 Jan, 2015 - Comments: 0

Ansys' Justin Nescott has extracted the top 5 engineering technology articles for 2014. Check out the turbocharged Dyson hand vac and the suspended animation trials. Mentor's J. VanDomelen looks at on-demand additive manufacturing on the International Space Station, otherwise known as 3D modeling and printing. It's a lot faster than waiting for a delivery. Cadence's Brian Fuller sits dow... » read more

Software-Driven Verification (Part 2)
By Brian Bailey - 05 Jan, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Blog Review: Dec. 31
By Ed Sperling - 31 Dec, 2014 - Comments: 0

Mentor's J. VanDomelen zeroes in on the two most interesting discoveries from the Philae comet landing. So what was that "eerie cyclical clicking" sound? Synopsys' Ray Varghese digs into basic coherent transaction testing for AXI/ACE compliant interconnects. You might want to put on another pot of coffee. Cadence's Brian Fuller offers some deep insights into synthesis, verification and te... » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 29 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

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