tag: verification

Blog Review: Jan. 2
By Ed Sperling - 02 Jan, 2014 - Comments: 0

ARM’s Lori Kate Smith has been scouring the market for cool devices. Her pick: the Epic Giveaway wrist computer for runners. She says the only drawback is the 10-hour battery life, but if you can run that long and still have some juice left in your body you probably need a GPS, instead. Mentor’s J VanDomelen has been tracking orders from the United Arab Emirates’ and its neighbors for ... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Top 5 Trends For 2014
By Frank Schirrmeister - 19 Dec, 2013 - Comments: 0

My daughter’s and my traditional yearly cookie baking party last weekend reminded me of two things: There is still no easy recipe for system design and verification and – of course – the year is almost over again. Ouch. Let’s look back at 2013 first. Earlier this year we held a System to Silicon Verification Summit in San Jose, with an interesting technical keynote by Brian Bailey an... » read more

Accelerating Functional Closure
By Various Writers - 18 Dec, 2013 - Comments: 0

This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when... » read more

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics
By David Hsu - 05 Dec, 2013 - Comments: 0

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confi... » read more

The Race For Better Verification
By Graham Bell - 21 Nov, 2013 - Comments: 0

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Coming Up With The Wrong Formal Answer
By Brian Bailey - 21 Nov, 2013 - Comments: 0

It was a surreal moment. I was sitting in a conference room in Portland listening to a panel session about [getkc id="33" kc_name="formal"] methods. The topic was discussing the fact that there is insufficient education at the undergraduate level in formal methods and algorithmic approaches to verification. You can read about the panel here. In the question and answer session, a point was ma... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 04 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: Debug
By Ed Sperling - 31 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

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