tag: verification

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification
By Abdellah Bakhali - 14 Apr, 2022 - Comments: 0

As the potential for complex interactions between voltage domains grows significantly with the increase in design density at each new process node, the complexity of spacing checks in design rule checking (DRC) also increases. To minimize these types of risk, many simple spacing checks have evolved to become voltage-aware DRC (VA-DRC) checks that incorporate voltage values to determine the requ... » read more

Automated DRC Voltage Annotation Provides Faster And More Accurate Verification For Voltage-Aware Spacing Rules
By Siemens EDA - 13 Apr, 2022 - Comments: 0

Accurate and repeatable reliability verification is now essential for both advanced node designs and the increasingly complex products being produced at established nodes. To ensure compliance with all process, reliability, and power management requirements, voltage-aware DRC applies variable spacing requirements, based on either the absolute voltage or delta voltage values, to accurately evalu... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards
By Cadence - 13 Apr, 2022 - Comments: 0

By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

Verification Management For Aerospace And Defense
By Siemens EDA - 07 Apr, 2022 - Comments: 0

This executive brief presents the verification management digital thread. It demonstrates the value of integrated verification and certification for accelerating product delivery in the aerospace and defense industry. Read the brief to learn how you can certify products on schedule and within budget, eliminating the silos in your verification and certification activities. Aircraft certificat... » read more

EDA On Cloud Presents Unique Challenges
By Ann Mutschler - 31 Mar, 2022 - Comments: 0

Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

How To Justify A Data Center
By Ann Mutschler - 24 Mar, 2022 - Comments: 0

The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

Improve Your Verification Methodology: Hunt Bugs Flying In Squadrons
By Philippe Luc - 24 Mar, 2022 - Comments: 0

After analyzing bugs on several generations of CPUs, I came to the conclusion that “bugs fly in squadrons.” In other words, when a bug is found in a given area of the design, the probability that there are other bugs with similar conditions, in the same area of the design, is quite high. Processor bugs don’t fly alone Finding a CPU bug is always satisfying, however it should not be an e... » read more

Siemens EDA’s Full-Flow Portfolio Helps Engineers Achieve Optimum IC Design Verification Efficiency
By Siemens EDA - 24 Mar, 2022 - Comments: 0

A quick overview of the front-end flow using the S-Edit schematic capture environment will be covered in this white paper, followed by a more detailed description and steps for using the Analog FastSPICE (AFS) platform simulator to go through the verification of a basic amplifier design. Greater efficiency in analog design verification can now be achieved using our enhanced inter-tool commun... » read more

Shifting The Design Paradigm To Improve Verification Efficiency
By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Why Comparing Processors Is So Difficult
By Brian Bailey - 10 Mar, 2022 - Comments: 2

Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

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