tag: verification

How To Justify A Data Center
By Ann Mutschler - 24 Mar, 2022 - Comments: 0

The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

Improve Your Verification Methodology: Hunt Bugs Flying In Squadrons
By Philippe Luc - 24 Mar, 2022 - Comments: 0

After analyzing bugs on several generations of CPUs, I came to the conclusion that “bugs fly in squadrons.” In other words, when a bug is found in a given area of the design, the probability that there are other bugs with similar conditions, in the same area of the design, is quite high. Processor bugs don’t fly alone Finding a CPU bug is always satisfying, however it should not be an e... » read more

Siemens EDA’s Full-Flow Portfolio Helps Engineers Achieve Optimum IC Design Verification Efficiency
By Siemens EDA - 24 Mar, 2022 - Comments: 0

A quick overview of the front-end flow using the S-Edit schematic capture environment will be covered in this white paper, followed by a more detailed description and steps for using the Analog FastSPICE (AFS) platform simulator to go through the verification of a basic amplifier design. Greater efficiency in analog design verification can now be achieved using our enhanced inter-tool commun... » read more

Shifting The Design Paradigm To Improve Verification Efficiency
By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Why Comparing Processors Is So Difficult
By Brian Bailey - 10 Mar, 2022 - Comments: 2

Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Who Will Own Debug?
By Hagai Arbel - 09 Mar, 2022 - Comments: 0

Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years. While we’ve exchanged many ideas about EDA and innovation, one sentence that he said stays in my head: Whoever will own debug, will own th... » read more

Why Traceability Matters
By Ed Sperling - 02 Mar, 2022 - Comments: 0

More heterogeneous and increasingly dense chip designs make it much harder to stay on track with initial specifications. Paul Graykowski, senior technical marketing manager at Arteris IP, talks about matching requirements to the design, the impact of ECOs and other last-minute changes, and best practices for managing revisions. » read more

Preparing For Test Early In The Design Flow
By Ann Mutschler - 02 Mar, 2022 - Comments: 0

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Intelligent Waveform Replay For Efficient Debug
By Taruna Reddy - 24 Feb, 2022 - Comments: 0

There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

Addressing Library Characterization And Verification Challenges Using ML
By Siemens EDA - 23 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

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