tag: verification

Intelligent Waveform Replay For Efficient Debug
By Taruna Reddy - 24 Feb, 2022 - Comments: 0

There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

Addressing Library Characterization And Verification Challenges Using ML
By Siemens EDA - 23 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis
By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?
By Joseph Hupcey III - 03 Feb, 2022 - Comments: 0

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero risk of unwanted surprises escaping undetected into your end-product. In order of high-to-low probability, consider: The presence of a weird-yet-entirely-possible corner-case bug Bugs “insid... » read more

Verification Signoff Beyond Coverage
By Paul Graykowski - 03 Feb, 2022 - Comments: 0

A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. Th... » read more

Addressing Library Characterization And Verification Challenges Using ML
By Siemens EDA - 02 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Ethical Coverage
By Brian Bailey - 27 Jan, 2022 - Comments: 1

How many times have you heard statements such as, "The verification task quadruples when the design size doubles?" The implication is that every register bit that is created has doubled the state space of the design. It gives the impression that complete verification is hopeless, and because of that little progress has been made in coming up with real coverage metrics. When constrained rando... » read more

Greener Design Verification
By Brian Bailey - 27 Jan, 2022 - Comments: 0

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, or power consumption. Admittedly, one is a per unit cost while the other is a development cost, but could the industry be doing more to make development greener? It can take days for regression... » read more

Dependable Verification Is The Foundation ICs Require
By Pirzad Motafram - 27 Jan, 2022 - Comments: 0

As our world becomes increasingly high-tech, it is easy to lose sight of the little things that make all of our fancy gadgets achieve optimal performance. The one thread that enables you to get all of the benefits of a new laptop, tablet, smartphone, or your automobile’s digital dashboard and connects the components that ensure best performance is the integrated circuit (IC). For as breath... » read more

FortifyIQ: Hardware Security Verification
By Zoya Hasan - 18 Jan, 2022 - Comments: 0

What’s the best way to protect against side-channel attacks? FortifyIQ believes the answer lies at least partly in the verification process. Side channel and fault-injection attacks have been garnering more attention lately as hackers continue to branch out from software to a combination of software and hardware. This is especially worrying for safety-critical applications, such as automot... » read more

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