tag: verification

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug
By Siemens EDA - 08 Sep, 2021 - Comments: 1

Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

A New Vision For Memory Chip Design And Verification
By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Four Requirements To Improve Chip Design Debug
By Taruna Reddy - 26 Aug, 2021 - Comments: 0

Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Working With RISC-V
By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

Now You Can Automate Latch-Up Verification For 2.5/3D Technologies
By Dina Medhat - 12 Aug, 2021 - Comments: 0

Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC). It may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). To protect against latch-up conditions, there are two key types of latch-up design rules—fundamental and advanced [1,2]. Fundamental rules are the local latch-up design r... » read more

2.5D And 3D-IC Latch-Up Prevention
By Siemens EDA - 11 Aug, 2021 - Comments: 0

2.5D/3D ICs have evolved into an innovative solution for many design and integration situations, but they present unique verification obstacles that challenge electronic design automation (EDA) tools originally designed for 2D ICs. Automated solutions are needed not only to reduce verification cycles but also to improve the quality and reliability of package designs. Automated verification o... » read more

10X Higher Productivity With VCS Dynamic Test Loading
By Synopsys - 11 Aug, 2021 - Comments: 0

The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve t... » read more

Beyond Bug Hunting: Verification Coverage From Safety To Certification
By OneSpin Solutions - 04 Aug, 2021 - Comments: 0

Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Co... » read more

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
By Lee Moore - 29 Jul, 2021 - Comments: 1

By Lee Moore and Simon Davidmann The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating... » read more

Robust Variation-Aware Smart Power Designs For Silicon Success
By Nebabie Kebebew - 29 Jul, 2021 - Comments: 0

Power management ICs (PMICs) is a rapidly growing segment in the semiconductor industry. The growth has been fueled by the demand for Smart Power applications that include wearable electronics, mobile computing platforms, printers, hard disk drives (HDD), IoT devices, and the full array of automotive applications. According to a report from market research firm Coherent Market Insights, the gl... » read more

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