tag: verification

Building A State-of-the-Art Verification Environment
By Cadence - 08 Jan, 2020 - Comments: 0

The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

Applications, Ecosystems And System Complexity Will Be Key Verification Drivers For 2020
By Frank Schirrmeister - 19 Dec, 2019 - Comments: 0

In my predictions blog last year, I focused on verification throughput and its expected growth in 2019. The four areas I predicted we’d see growth in during 2019 were scalable performance, unbound capacity including cloud enablement, smart bug hunting and multi-level abstractions. In 2018, the five key verification drivers that I identified were security, safety, application specificity, proc... » read more

Will Open-Source Processors Cause A Verification Shift?
By Ann Mutschler - 19 Dec, 2019 - Comments: 0

While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows... » read more

When Is Robustness Verification Complete?
By Janusz Kitel - 19 Dec, 2019 - Comments: 0

Understandably, hardware designed for an aircraft, or indeed any safety critical application, must be robust. I also believe that all engineers wish to verify their designs as thoroughly as possible, anyway. However, there are limiting factors; most notably the high complexity of most designs. Since we are unable to discover and verify the design against all abnormal conditions, the main questi... » read more

Verifying Security In Processor-based SoCs
By Ruud Derwig - 12 Dec, 2019 - Comments: 0

By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

Interdependencies Complicate IC Power Grid Design
By Ann Mutschler - 12 Dec, 2019 - Comments: 0

Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform
By Synopsys - 11 Dec, 2019 - Comments: 0

It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Achieving Functional Safety For Autonomous Vehicle SoC Designs
By Mentor, a Siemens Business - 03 Dec, 2019 - Comments: 0

Autonomous vehicle systems will be expected to meet rigorous safety standards regarding many aspects of system design and performance. One set of these standards, known as functional safety, focuses on the safety and reliability of the electrical and electronic systems within the vehicle, and the system-on-chip (SoC) devices in particular. As the complexity of these devices grows, autonomous ve... » read more

Finding Hardware Trojans
By Ed Sperling - 03 Dec, 2019 - Comments: 0

John Hallman, product manager for trust and security at OneSpin Technologies, looks at how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised. » read more

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