Reduce 3D-IC Design Complexity: Early Package Assembly Verification

By Siemens EDA - 24 Apr, 2024 - Comments: 0

Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D-IC design in this new technical paper. As 2.5D and 3D-ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process. What you'll learn: Overcom... » read more

Scalable Verification of Memory Consistency (Purdue University)

By Technical Paper Link - 06 Apr, 2024 - Comments: 0

A new technical paper titled "QED: Scalable Verification of Hardware Memory Consistency" was published by researchers at Purdue University. Abstract "Memory consistency model (MCM) issues in out-of-order-issue microprocessor-based shared-memory systems are notoriously non-intuitive and a source of hardware design bugs. Prior hardware verification work is limited to in-order-issue processors... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?

By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix. Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

Navigating Design Challenges

By Siemens EDA - 28 Mar, 2024 - Comments: 0

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

LLMs For EDA, HW Design and Security

By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A new technical paper titled "Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge" was published by researchers at Kansas State University, University of Science and Technology of China, Michigan Technological University, Washington University in St. Louis and Silicon Assurance. Abstract "In the rapidly evolving semiconductor industry, where research, design... » read more

Overcoming The Challenges Of Verifying Multi-Die Systems

By Synopsys - 12 Mar, 2024 - Comments: 0

Despite clear advantages of multi-die systems, the decision to design a multi-die system rather than a traditional monolithic SoC is not easy. There are numerous new challenges that stand in the way of multi-die system realization. This white paper focuses on the verification challenges of multi-die systems, including: Addressing capacity and performance for system verification Valid... » read more

Accellera Preps New Standard For Clock-Domain Crossing

By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Weak Verification Plans Lead To Project Disarray

By Anika Sunda - 29 Feb, 2024 - Comments: 0

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified. It’s a big responsibility! Getting it right means having a good blueprint for verification closure. However, getting it wrong could result in bug escapes, wasting of resources, and possibly lead to a device failing altogether. With the foc... » read more

A Game-Changer For IP Designers: Design-Stage Verification

By Siemens EDA - 28 Feb, 2024 - Comments: 0

Discover how to transform your IP design process with the Calibre Shift left initiative. In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, a... » read more

Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs

By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: verification