tag: verification

Design For Airborne Electronics
By Ann Mutschler - 03 Feb, 2020 - Comments: 0

The Next Generation Air Transportation System (NextGen), an FAA-led modernization of America's air transportation system meant to make flying more efficient, predictable and safer, is currently underway as one of the most ambitious infrastructure projects in U.S. history. This is not just a minor upgrade to an aging infrastructure. The FAA and partners are in the process of implementing new ... » read more

Balancing Flexibility And Quality In SRAM Verification
By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Making Sure RISC-V Designs Work As Expected
By Ann Mutschler - 30 Jan, 2020 - Comments: 0

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

2019 – The Year Of The “Dynamic Duo” Of Emulation and Prototyping
By Frank Schirrmeister - 30 Jan, 2020 - Comments: 0

In technology, we are always trying to figure out when we have reached critical mass, have crossed the chasm, or even can be considered mainstream. We all have seen the adoption curves for consumer products. In design and verification technology, a distinct B2B setting with fewer end customers than in the B2C domain, the situation seems to be even worse as there is no “one flow” to design a... » read more

Big Design, IP and End Market Shifts In 2020
By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking
By Mentor, a Siemens Business - 29 Jan, 2020 - Comments: 0

A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

Random Directed Low Power Coverage Methodology
By Mentor, a Siemens Business - 15 Jan, 2020 - Comments: 0

This paper proposes a low-power coverage methodology based on the recently introduced UPF 3.0 low-power information model HDL package. Verification engineers can use this approach to achieve low-power coverage closure earlier. We share relevant case studies and examples using the methodology to solve low-power verification problems. It also discusses the benefits of this approach and its advant... » read more

Big Growth Areas: Connectivity, AI, Reliability
By Brian Bailey - 14 Jan, 2020 - Comments: 0

Connectivity and artificial intelligence (AI) will be the biggest drivers for 2020, with an emphasis on improved reliability across all areas. New standards, new applications, and new pressures being placed on old technology will created boundless opportunities for those ready to fill the need. Of course, there will also be a lot of carnage along the way, and we can expect to see a lot of that ... » read more

Using Automotive IP For Easier Integration Of Safety Into SoCs
By Shivakumar Chonnad - 09 Jan, 2020 - Comments: 0

By Shivakumar Chonnad and Vladimir Litovtchenko Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of S... » read more

Building A State-of-the-Art Verification Environment
By Cadence - 08 Jan, 2020 - Comments: 0

The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

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