Low Power Apps: Shaping The Future Of Low Power Verification


This paper describes how verification and design engineers can make use of UPF 3.0 information model-based HDL and Tcl APIs to write useful low-power apps. We present low-power apps that can be used to solve complex verification issues and provide case studies and examples to demonstrate usage. To read more, click here. » read more

Week in Review: Design, Low Power


The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Designing Networking Chips


Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Automotive IC Design Demands Next-Generation High-Sigma Verification


By Jeff Dyck High-sigma analysis is required for verifying replicated components, like memory blocks and standard cells, and for demonstrating mission-critical reliability for automotive and medical applications. It is not feasible to verify to high-sigma using brute-force Monte Carlo, as this requires 10s of millions of simulations to reach 5-sigma and billions in order to reach 6-sigma. S... » read more

Can AI, 5G Chips Be Verified?


AI and 5G bode well for the semiconductor industry. They will require many billions of new, semi-customized and highly complex chips from the edge all the way to the data center, and they will require massive amounts of engineering time and tooling. But these technologies also are raising lots of questions on the design and verification front about what else can be automated and how to do it. ... » read more

Will Top-Down Hardware/Software Co-Design Ever Happen?


Hardware/software co-design has been talked about, and predicted to be a problem, for at least two decades now. Why has the hardware/software development world not come to an end? In 1999, Wilf Corrigan—LSI Logic’s CEO at the time—said that the most pressing need for new EDA tools was a better methodology that would “allow software developers to begin software verification more near the... » read more

Pushing AI Into The Mainstream


Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible. But how deeply AI penetrates different market segments and technologies, and how quickly it pushes into the mainstream, depend on a variety of issues that still must be resolved. In addition to a plethora of techni... » read more

Connectivity Checking Is A Perfect Fit For Formal Verification


Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these app... » read more

Verifying AI Designs Thoroughly And Quickly


You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

A Simplified Way to Debug IIP Designs and SoC


Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

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