tag: verification

Design For Advanced Packaging
By Brian Bailey - 08 Nov, 2018 - Comments: 0

Advanced packaging techniques are viewed as either a replacement for Moore's Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can be manufactured with sufficient yield and the amount of attention being paid to the demands advanced packaging has on the design and verification flows. Not all advanced packaging places the same... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Reduction In First Silicon Success
By Brian Bailey - 25 Oct, 2018 - Comments: 0

Every two years, Harry Foster, chief scientist for Mentor, a Siemens Business, works with Wilson Research to do a verification study. Those studies have influenced many in the industry, indicating where users are experiencing the most pain, spending their time, growing their team sizes and where money would be best spent. However, over the past four years, the ASIC industry has basically been i... » read more

Integrating Results And Coverage From Simulation And Formal
By Tom Anderson - 25 Oct, 2018 - Comments: 0

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

Linting With ALINT-PRO Within Active-HDL
By Aldec - 24 Oct, 2018 - Comments: 0

Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

Re-using Common Simulation Set-Up Processes To Speed Regression
By Rohit Jain - 11 Oct, 2018 - Comments: 0

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs
By Himanshu Bhatt - 11 Oct, 2018 - Comments: 0

With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

Reliability, Machine Learning And Advanced Packaging
By Ed Sperling - 11 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Planning Out Verification
By Ed Sperling - 28 Sep, 2018 - Comments: 0

OneSpin Solutions’ Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow. https://youtu.be/2zrgaq2I1SQ » read more

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