tag: verification

Preparing For The IoT Data Tsunami
By Ann Mutschler - 29 Feb, 2016 - Comments: 0

Engineering teams are facing a flood of data that will be generated by the [getkc id="76" comment="Internet of Things"], both from the chip design side and from the infrastructure required to handle that data. There are several factors that make this problem particularly difficult to deal with. First, there is no single data type, which means data has to be translated somehow into a usable f... » read more

Racing To Design Chips Faster
By Ed Sperling - 25 Feb, 2016 - Comments: 6

A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

The Ultimate Shift Left
By Anupam Bakshi - 25 Feb, 2016 - Comments: 0

Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several semiconductor development teams, especially those in Fortune 500 companies, who do not have time to change their design process. They often cite various reasons such as: • Too busy with the current project. • What we have is working, so... » read more

Education And Communication
By Frank Schirrmeister - 25 Feb, 2016 - Comments: 0

With the System Development Suite introduced back in 2011, it is worthwhile to review how the adoption of the connected verification engines has progressed. It turns out that only part of the issues to be solved are purely technical. Communication across different technology areas is key, and with that, education of a new breed of engineer may become a key issue going forward. As a son of a ... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

Managing Validation And Verification Abstract Activities For DO-254
By Aldec - 24 Feb, 2016 - Comments: 0

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

A Winning Formula
By Lauro Rizzatti - 22 Feb, 2016 - Comments: 0

It may be fitting that DVCon will be held the same week as Super Tuesday this year, the day when the greatest number of states in the U.S. hold primary elections. Big dollar expenditures and return on investment (ROI) strategies are part of today’s political landscape, as they are with chip design and verification. Missing a delivery window for an electronics device can cost 25% or more o... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly
By Mentor, a Siemens Business - 18 Feb, 2016 - Comments: 0

Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

Debug Becomes A Bigger Problem
By Brian Bailey - 11 Feb, 2016 - Comments: 3

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

Automating Coverage And Analysis Of Low Power Designs
By Ellie Burns - 11 Feb, 2016 - Comments: 0

There are some exciting new things in the just released IEEE1801-2015 (aka UPF 3.0), some of which have significant benefits for coverage of low power designs, which is what we’ll be looking at in this blog. One of these is improved semantics for the add power state command, introduced in IEEE1801-2009 (aka UPF 2.0). These clarifications to the add power state command allow you to clearly ... » read more

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