tag: verification

Enhancing Automotive Electronics Reliability Checking
By Mentor, a Siemens Business - 11 Nov, 2015 - Comments: 0

While complexity in the automotive electronics space continues to increase, ensuring reliability in safety-critical systems is crucial to the success and reputation of the automotive industry. Automation of complex reliability verification tasks provides a robust and repeatable mechanism for building reliable automotive IC designs within market-driven schedules. Utilizing advanced reliability v... » read more

Stop Getting Burned By Power Consumption Surprises
By Alan Gibbons - 09 Nov, 2015 - Comments: 0

Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issue... » read more

The Cloud, The IoE, And You
By Ernest Worthman - 05 Nov, 2015 - Comments: 0

If you’re anywhere in the high-tech biz, the two terms that are rocking your world are the Internet of Everything and the Cloud. Whether you are on the inside track of these, or on the sidelines, they are going to be two of the most disruptive technologies of the 21st century. The cloud is already here and gaining momentum. Some people will argue that the cloud has been here since the ince... » read more

SoC Verification For The Internet of Things
By Mentor, a Siemens Business - 04 Nov, 2015 - Comments: 0

Larger, more complex designs with more software and tighter power budgets require new verification solutions that target the associated technological challenges. This paper explores why traditional digital simulation and hardware prototypes fall short when it comes to verifying IoT and network designs, why using emulation is critical for a total verification solution, and why traditional in-cir... » read more

The New Face of Formal
By Brian Bailey - 04 Nov, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

Hybrid Emulation Gets More Hybrid
By Ed Sperling - 29 Oct, 2015 - Comments: 0

Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

Requirements For Datacenter-Ready Emulation
By Frank Schirrmeister - 29 Oct, 2015 - Comments: 0

It’s time to look at what the latest trends in emulation are and to review some of the key requirements to make it datacenter-ready. Specifically, I will look at virtualization of external interfaces as well as emulation throughput, specifically the allocation of jobs into emulators. One overarching trend in verification lies in the connection of the engines in what Jim Hogan has dubbed t... » read more

Improving Emulation Throughput For Multi-Project SoC Designs
By Cadence - 28 Oct, 2015 - Comments: 0

As design sizes grow, so, too, does the verification effort. Indeed, verification has become the biggest challenge in SoC development, representing a majority share of the development cost, both for hardware itself and for verification at the hardware/software interface. And today, it’s not uncommon for companies to have distributed teams working on multiple SoC designs in parallel. In some c... » read more

All-in-C Behavioral Synthesis And Verification
By Aldec - 28 Oct, 2015 - Comments: 0

This paper presents the benefits of C language-based behavioral synthesis design methodology over traditional RTL-based methods for System LSI, or SoC designs. A comprehensive C-based tool flow, based on CyberWorkBench®, developed during the last twenty years at NEC’s R&D laboratories is introduced. This includes behavioral synthesis and formal verification and hardware-software co-simulatio... » read more

Will The Chip Work?
By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

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