tag: verification

Full Coverage Or Full Monty?
By Brian Bailey - 09 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Toward Smarter Design Automation
By Frank Schirrmeister - 28 May, 2015 - Comments: 0

In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more

Tech Talk: Power Tools
By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

Automating Root-Cause Analysis To Reduce Time To Find Bugs by Up To 50%
By Cadence - 27 May, 2015 - Comments: 0

If you’re spending more than 50% of your verification effort in debug, you’re not alone. For many design, verification, and embedded software engineers as well as engineers verifying complex standard protocols, debug is the primary bottleneck in verification. Most debug today is completed using the traditional methodology of print statements paired with waveforms. Given that today’s desig... » read more

A Fireside Chat With Imagination On Hardware-Assisted Development And Emulation
By Frank Schirrmeister - 13 May, 2015 - Comments: 0

During one of my trips to Europe I was able to sit down with Colin McKellar, senior director of hardware engineering at Imagination Technologies. He is my main contact for all things verification at Imagination. Imagination’s product challenges include maintaining the level of quality of their IP products within shorter timelines and dealing with integration of their IP into more complex c... » read more

Tech Talk: Faster SPICE
By Ed Sperling - 04 May, 2015 - Comments: 0

ProPlus CTO Bruce McGaughy explains why FastSPICE (fast Simulation Program with Integrated Circuit Emphasis) is running out of steam in the finFET generation and what needs to happen next. [youtube vid=07XzUQxPUr8] » read more

What Not To Verify
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

It is well understood that [getkc id="10" kc_name="verification"] is all about mitigating and managing risk, and success here begins with a good verification planning process. During the planning process, the project team creates a list of specific design functions and use cases that must be verified—and they identify the technique used to verify each specific item on the list. That list c... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

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