tag: verification

Keeping Up With The Productivity Challenge
By Brian Bailey - 06 Nov, 2014 - Comments: 3

Until recently, EDA software rode the coattails of increasing processor performance as part of its drive to continue providing faster and more powerful development software to the people designing, among other things, the next generation of faster processors. It was a fortuitous ring. Around the turn of the century, with the migration to multi-core computing systems, all of that changed. In ord... » read more

A Formally Free Lunch
By Brian Bailey - 05 Nov, 2014 - Comments: 0

I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

Automated Assertion-Based Verification Methodologies For IP And SoC Development
By Atrenta - 05 Nov, 2014 - Comments: 0

The rapid growth in complexity and size of modern System on Chip devices (SoCs), along with the expense of developing these ICs, has driven the need for design reusability. Today, SoC designs are typically built as a collection of individual IP (Intellectual Property) blocks stitched together with glue logic. These IP can be sourced from multiple design teams, including many 3rd-party teams. So... » read more

Extending Digital Verification Techniques For Mixed-Signal SoCs With VCS AMS
By Synopsys - 22 Oct, 2014 - Comments: 0

The growth in mixed-signal system-on-chip (SoC) designs is driven by many factors, including cost, performance and power consumption. This is fueled by many industry segments, including mobile communication, automotive, imaging, medical, networking and power management. The convergence of analog and digital blocks within the same die is driving the need for SoC design teams to adopt new verific... » read more

Top 10 Ways To Automate Verification
By Cadence - 22 Oct, 2014 - Comments: 0

It’s a persistent theme: engineers are expected to do more with the same or fewer resources. Meantime, designs continue to grow larger and more complex. Studies have shown that verification continues to consume up to 70% of the IC development cost in each advanced node. Cadence’s R&D teams designed the latest version of the Incisive® functional verification platform with these pressures in... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 16 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Memory Directions Uncertain
By Brian Bailey - 09 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Energy Boost For Power Standards
By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

The Week In Review: Design
By Ed Sperling - 26 Sep, 2014 - Comments: 0

Tools Synopsys rolled out a hybrid verification platform, which it said can shave months off design time. The platform acts like a bridge between emulation, FPGA prototyping, simulation, static and formal verification and debug. Mentor Graphics uncorked a new version of its embedded hypervisor, which includes better system configuration, debugging and hardware support. The hypervisor is aim... » read more

How To Cut Verification Costs For IoT
By Brian Bailey - 25 Sep, 2014 - Comments: 0

Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

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