tag: verification

Blog Review: July 22
By Jesse Allen - 22 Jul, 2015 - Comments: 0

It's been a hot summer for high-level synthesis, says Cadence's Dave Pursley in a collection of the season's HLS highlights spanning DAC to SystemC Japan. Mentor's Harry Foster continues his survey of functional verification with a look at the adoption trends of various verification technologies, and the reasons one-third of projects use emulation or FPGA prototyping. Synopsys' Navraj Nan... » read more

Power Breaks Everything
By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

SoC Connectivity Verification Nightmare
By Kiran Vittal - 09 Jul, 2015 - Comments: 0

At the recent 2015 women’s World Cup soccer final in Canada, Japan was completely caught off guard in the first 15 minutes (and 4 seconds) by the USA. They were wary of the “set-piece” play by the USA team, which they were not able to defend against, resulting in the first three goals by the American women. However, the game breaker was the 54-foot midfield hat-trick goal from Carli Lloyd... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Wrong Verification Revolution Offered
By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

Towards A Metric To Measure Verification Computing Efficiency
By Frank Schirrmeister - 25 Jun, 2015 - Comments: 1

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

Shift Left: Software Or Hardware?
By Tom De Schutter - 25 Jun, 2015 - Comments: 0

A couple of weeks ago I was with a virtual prototyping user who described the benefits his company has seen from deploying virtual prototyping for early software development. The use of virtual prototyping has been rolled out progressively to more projects over the years, making it possible for the company to measure its impact on the software availability schedule and the impact has been drama... » read more

Interoperable Application-Specific Solutions For Formal Verification
By Cadence - 24 Jun, 2015 - Comments: 1

Historically, formal verification technology has been licensed as a compre- hensive suite of tools that can be used to address a broad range of formal verification applications and problems. Such deployment required a wide range of in-depth skills on the user’s part before the technology could be leveraged by not only first time users, but also experienced ones. New users were often overwhelm... » read more

Full Coverage Or Full Monty
By Brian Bailey - 22 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Power Verification Now Required
By Ann Mutschler - 17 Jun, 2015 - Comments: 0

Today’s verification tasks may seem daunting — and much of it is — but all of it is absolutely necessary to make sure chips operate properly with a larger system. Throw power into the mix and the challenges mount. The good news is that there is no shortage of tools and methodologies to help with these tasks. The bad news is that even the best tools won’t make the challenges disappear... » read more

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