tag: VLSI Research

Multi-Patterning EUV Vs. High-NA EUV
By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2019 - Comments: 0

Arm's Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated. Cadence's Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA too... » read more

Blog Review: Nov. 27
By Jesse Allen - 27 Nov, 2019 - Comments: 0

Arm's Ben Fletcher digs into what's needed to make wireless 3D integration a reality from a tool to automate the design and optimization process for inductors used in wireless 3D-ICs to exploring how the data can be encoded in the transceiver to reduce power consumption. Cadence's Paul McLellan listens in as Eli Singerman of Intel explains the importance of platform security and why firmware... » read more

DRAM Scaling Challenges Grow
By Mark LaPedus - 21 Nov, 2019 - Comments: 5

DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

Blog Review: Nov. 20
By Jesse Allen - 20 Nov, 2019 - Comments: 0

Arm's Ben Fletcher points to research into a new low-cost alternative to through-silicon vias in 3D stacked ICs, particularly cost-sensitive IoT designs, where communication between silicon layers is completely wireless. Cadence's Paul McLellan checks in on the progress of DARPA's OpenROAD project to build a no-human-in-the-loop open source EDA flow for leading-edge nodes. Mentor's Colin ... » read more

Blog Review: Oct. 9
By Jesse Allen - 09 Oct, 2019 - Comments: 0

In a video, Cadence's Tom Hackett continues his introduction to finite element analysis (FEA) and the important role it can play in electronics deign. Mentor's Colin Walls considers dynamic memory allocation in real-time operating systems and the problems of non-deterministic behavior and ill-defined failure modes. Synopsys' Taylor Armerding contends that ethical hackers are a necessary p... » read more

Challenges Grow For Finding Chip Defects
By Mark LaPedus - 19 Sep, 2019 - Comments: 5

Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Using Machine Learning In Fabs
By Mark LaPedus - 19 Sep, 2019 - Comments: 1

Amid the shift towards more complex chips at advanced nodes, many chipmakers are exploring or turning to advanced forms of machine learning to help solve some big challenges in IC production. A subset of artificial intelligence (AI), machine learning, uses advanced algorithms in systems to recognize patterns in data as well as to learn and make predictions about the information. In the fab, ... » read more

Blog Review: Aug. 28
By Jesse Allen - 28 Aug, 2019 - Comments: 0

Cadence's Paul McLellan takes a look at the numerous challenges in designing and manufacturing Cerebras' massive 400,000 processor, 1.2 trillion transistor chip. Synopsys' Taylor Armerding points to a lack of robust mobile app security and why building in security from the beginning can lead to greater productivity and cost saving. Mentor's Paul Johnston takes a look at what's in store at... » read more

Blog Review: Aug. 21
By Jesse Allen - 21 Aug, 2019 - Comments: 0

Cadence's Paul McLellan considers the path to autonomous vehicles and the many barriers that stand in the way. Mentor's Colin Walls notes that the fundamental function of an RTOS is to give the developer control of time and points to some of the time oriented services that assist. Synopsys' Taylor Armerding points to ways the financial services industry could improve cybersecurity, from u... » read more

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