tag: warpage

Growing Challenges With Wafer Bump Inspection
By Ed Sperling - 11 Oct, 2021 - Comments: 1

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes
By Brewer Science - 14 Aug, 2019 - Comments: 0

Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Material Solutions For FOWLP Die Shift And Wafer Warpage
By Shelly Fowler - 20 Jun, 2019 - Comments: 0

By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science
By Kim Yess - 10 Sep, 2018 - Comments: 0

Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

Tech Talk: Shrink Vs. Package
By Ed Sperling - 10 May, 2018 - Comments: 0

Andy Heinig, group manager for system integration at Fraunhofer EAS, talks about the tradeoffs between planar design and advanced packaging, including different types of interposers, chiplets and thermal issues. https://youtu.be/1BDqgCujJno » read more

Cheaper Fan-Outs Ahead
By Mark LaPedus - 07 Aug, 2017 - Comments: 6

Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package
By STATS ChipPAC - 08 May, 2017 - Comments: 0

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

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