tag: yield

New Technologies To Support 3D-ICs
By Brian Bailey - 04 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Wanted: More Fab Tool Part Standards
By Mark LaPedus - 15 Aug, 2019 - Comments: 0

As chipmakers ramp up the next wave of processes and grapple with how to reduce defect levels, they are encountering problems from an unlikely source—components inside of the fab equipment. Defects are unwanted deviations in chips, which impact yields and device performance. Typically, they are caused by an unforeseen glitch during the process flow. But a lesser-known problem involves defe... » read more

Process Window Optimization
By Ed Sperling - 07 Aug, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. » read more

Yield Impact For Wafer Shape Misregistration-Based Binning For Overlay APC Diagnostic Enhancement
By KLA - 05 Aug, 2019 - Comments: 0

By David Jayez, Kevin Jock, Yue Zhou and Venugopal Govindarajulu of GlobalFoundries, and Zhen Zhang, Fatima Anis, Felipe Tijiwa-Birk and Shivam Agarwal of KLA. 1. ABSTRACT The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pur... » read more

Big Shifts In Big Data
By Ed Sperling - 09 Jul, 2019 - Comments: 0

The big data market is in a state of upheaval as companies begin shifting their data strategies from "nothing" or "everything" in the cloud to a strategic mix, squeezing out middle-market players and changing what gets shared, how that data is used, and how best to secure it. This has broad implications for the whole semiconductor supply chain, because in many cases it paves the way for ... » read more

Advanced Process Control
By Ed Sperling - 20 Jun, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Using ML For Post-Silicon Validation
By Ed Sperling - 11 Jun, 2019 - Comments: 0

Ira Leventhal, vice president of Advantest’s new concept product initiative, talks about how to use machine learning to ferret out hidden relationships in a complex design and to utilize that data to improve chips. » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 May, 2019 - Comments: 0

M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing
By Pradeep Nanja - 23 May, 2019 - Comments: 0

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

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