tag: yield

Controlling IC Manufacturing Processes For Yield
By Ed Sperling - 24 Apr, 2019 - Comments: 0

Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control
By Benjamin Vincent - 25 Mar, 2019 - Comments: 0

Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

E-Beam Review And CD Measurement Revolutionizes Display Yield Management
By Applied Materials - 20 Mar, 2019 - Comments: 0

Fundamental changes are occurring in the display industry, driven by demands for higher-resolution screens and other capabilities for both mobile and TV applications. To meet these demands, the display technology roadmap in this article calls for innovations in materials, processes and device technology. Critical requirements include smaller design rules and the adoption of a range of materi... » read more

Using Sensor Data To Improve Yield And Uptime
By Ed Sperling - 21 Feb, 2019 - Comments: 2

Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

Lithography Challenges For Fan-out
By Mark LaPedus - 12 Feb, 2019 - Comments: 3

Higher density fan-out packages are moving toward more complex structures with finer routing layers, all of which requires more capable lithography equipment and other tools. The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these critical dimensions (CDs), fan-outs will provide better per... » read more

AI In Chip Manufacturing
By Ed Sperling - 10 Jan, 2019 - Comments: 0

Ira Leventhal, New Concept Product Initiative vice president at Advantest, talks with Semiconductor Engineering about using analysis and deep learning to make test more efficient and more effective. https://youtu.be/3VVG4JVnjHo » read more

AI Training Chips
By Ed Sperling - 01 Nov, 2018 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering about how to architect an AI training chip, how different processing elements are used to accelerate training algorithms, and how to achieve improved performance. https://youtu.be/4cnBCX-9jlk     See other tech talk videos here. » read more

Variability In Chip Manufacturing
By Ed Sperling - 09 Oct, 2018 - Comments: 0

Brewer Science’s Jim Korich talks about how to deal with variability in processes and why consistency in materials is so important at advanced nodes. https://youtu.be/U1KkUmtmqpE » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Process Corner Explosion
By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy