Week In Review: Design, Low Power

NXP buys Marvell’s Wi-Fi biz; FPGA prototyping; yield analysis; early physical verification; IP characterization; ML/NN cores; PCIe 5.0.


NXP will acquire Marvell’s Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020.

Cadence unveiled a data center-optimized FPGA-based prototyping system, the Protium X1, which offers multi-MHz speed for early software development, hardware/software regressions and full system validation. Scalable up to 32 racks, it utilizes Xilinx Virtex UltraScale VU440 and provides 5MHz on billion-gate designs and up to 100MHz for single-FPGA designs. It also includes a unified front-end with the Palladium Z1 emulation platform. Nvidia deployed the Protium X1 for early software development of its large-capacity GPUs.

Synopsys revealed a new pre-silicon full-chip-scale parametric design yield analysis tool. PrimeYield uses fast statistical methods and machine learning technology that the company says provides 1000X faster performance than Monte Carlo static timing analysis. Using the core engines of PrimeTime signoff and HSPICE simulation tools, it identifies and drives optimization of yield-impacting cells caused by statistical correlation and sensitivity to various design variations, such as supply voltage drops or manufacturing variability.

Mentor added the Reconnaissance functionality to its Calibre tool for rapid physical verification of blocks and IC designs in the early development phase when large counts of DRC errors are common. The function targets a selected class of errors associated with systemic issues common in early design development and provides histograms, an SoC “heat map,” and filtering/sorting capabilities.

Silvaco uncorked a scalable IP characterization and modeling tool. Viola 10X is capable of modeling and characterizing standard cell libraries, I/O pad circuitry, and digital memories for designs targeted at nanometer process nodes. It automatically performs static structural analysis on transistor-level netlists of standard cells and complex custom cells or macros and incorporates SmartSpice simulator and Jivaro-A reduction technology.

Synopsys updated its Verification Continuum Platform, adding more native integrations across tools to provide up to 5X higher verification performance. Included are faster loading for simulation and debug; static verification, simulation, and debug integrations; a single compile and intelligent fault injection and scheduling for formal and functional qualification; and integrated VIP, emulation, and simulation supporting unified compile of design and testbench and low latency interface.

Arm debuted a suite of Arm IP that targets machine learning and neural network functionality. The first two processors in the family focus on mobile: the Arm ML processor delivers more than 4.6 TOPs with a further uplift of 2x-4x in effective throughput in real-world uses through intelligent data management, while the Object Detection (OD) processor is designed to efficiently identify people and other objects with real-time detection with Full HD processing at 60 fps and improved performance over traditional DSPs.

BrainChip debuted its Akida Neural Processing Core (NPC) IP targeting AI edge devices. The Akida NCP IP provides a neuromorphic fabric for spiking neural networks and includes multiple training modes, inference, and unsupervised learning for ASIC designs. A development environment is also available.

M31 Technology’s MIPI D-PHY RX and TX IP with built-in, hard CSI-2 controller has been integrated into Efinix’s Trion FPGA platform. The integration provides a multiple sets of unidirectional links with up to six Gbps per link to deliver a high-bandwidth interface for AI-driven FPGA markets.

Cadence’s full-flow digital and signoff tools support the new Arm Cortex-A77 CPU for high-performance, high-efficiency mobile applications, and a complete 7nm Rapid Adoption Kit (RAK) that utilizes Arm 7nm POP IP libraries is available.

Synopsys announced QuickStart Implementation Kits (QIKs) for Arm Cortex-A77 and Cortex-A55 in 7nm process technology using Arm Artisan Physical IP and POP IP. Synopsys’ design platform has been optimized for Arm’s Cortex-A77 CPU and Mali-G77 GPU.

The PCIe 5.0 standard has been released by PCI-SIG. The latest version can reach 32GT/s raw bit rate and up to 128 GB/s via x16 configuration. It also implements electrical changes to improve signal integrity and mechanical performance of connectors, has a new backwards compatible CEM connector targeted for add-in cards, and maintains backwards compatibility.

Mellanox Technologies adopted ANSYS’ power integrity and reliability signoff solutions for its finFET high-performance networking designs, including Ethernet and InfiniBand interconnect solutions. Mellanox cited enhanced capacity, accuracy and flexible resource utilization for block and full-chip flat signoff analysis.

AMD used Mentor’s Calibre nmDRC software platform for physical verification of its 7nm Radeon Instinct Vega20. Running on Azure using 69 HB-series virtual machines powered by 4,140 AMD EPYC processors, the pass took ~10 hours for the 13.2B transistor design.

Juniper Networks adopted Synopsys’ IC Compiler II place-and-route with Advanced Fusion for its next-generation 7nm SoC networking design comprised of billions of transistors. Juniper cited a 6% reduction in area and 14% power savings as well as ECO turnaround time reduction of over 40%.

eSilicon selected ANSYS’ multiphysics solutions for its next-generation system-in-package designs. eSilicon cited significant product performance, reliability and cost savings.

Astera Labs utilized Synopsys’ Fusion Design Platform, Verification Continuum Platform, and Design Services running on AWS to develop its PCIe 5.0 retimer for heterogenous compute and workload-optimized servers. Astera Labs cited an accelerated development schedule using the tools on the cloud.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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