tag: yield

Cleaning Data For Final Test
By Ed Sperling - 20 May, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about why data integrity is so critical for final test, what can cause it to be less-than-perfect, what’s needed to improve the quality of that data, and how that impacts the overall yield in a fab. » read more

Rising Packaging Complexity
By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

Holistic Yield Improvement Methodology
By PDF Solutions - 06 Apr, 2020 - Comments: 0

As new products and processes are being introduced into IC manufacturing at an accelerated rate, yield learning and ramping are becoming more challenging due to the increased interaction between the design and process. Compared to random defect caused yield losses, systematic yield loss mechanisms are becoming more important, thus initial yield ramping process becomes more challenging. A “hol... » read more

What’s WAT? Testing At The End Of Manufacturing
By Marie Ryan - 10 Mar, 2020 - Comments: 0

The high costs of building, resourcing and operating a foundry fabricating integrated circuits are well known. Fabless companies avoid this capital cost and focus on design and innovation in their area of expertise. On the other hand, the fabless company relies on the expertise and skills of the foundry to produce quality wafers. Many times a process used by a fabless company to manufacture... » read more

Wafer Test Challenges For Chiplets
By Amy Leong - 10 Mar, 2020 - Comments: 0

In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage. From a test perspective, making chiplets a mainstream technology depends on ensuring Good Enough Die at a reasonable test cost. Wafer-level test plays a critical and intricate role in the chipl... » read more

Chiplet Momentum Rising
By Mark LaPedus - 26 Feb, 2020 - Comments: 0

The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are rallying around the chiplet model, including AMD, Intel and TSMC. In addition, there is a new U.S. Department of Defense (DoD) initiative. The goal is to speed up time to market and reduce the cost... » read more

Scaling, Packaging, And Partitioning
By Ed Sperling - 17 Dec, 2019 - Comments: 0

Prior to the finFET era, most chipmakers either focused on shrinking or packaging, but they rarely did both. Going forward, the two will be inseparable, and that will lead to big challenges with partitioning of data and processing. The key driver here, of course, is that device scaling no longer provides appreciable benefits in power, performance and cost. Nevertheless, scaling does provide ... » read more

A Holistic Approach To Yield Management
By Marie Ryan - 10 Dec, 2019 - Comments: 0

At yieldHUB we work with consultants and semiconductor experts, like André van de Geijn, semiconductor expert and author of Collaboratism. He supports our customers on the west coast of the US. We asked him about the benefits of various yield management solutions (YMS). In this article we will explain the benefits with insights from André. Today, people look at their current problem an... » read more

Die-To-Die Connectivity
By Ed Sperling - 22 Nov, 2019 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

The Challenge Of Defining Worst Case
By Brian Bailey - 14 Nov, 2019 - Comments: 0

Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

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