Testing Silicon Photonics In Production

As silicon photonics costs come down, the technology is being worked into new applications, from connectivity to AI. But full commercial production requires testing those photonic circuits before shipping them.

Photonics testing is only getting started. Volume production is still not happening, and test equipment and techniques are still being developed. What exists today is a blend of existing semiconductor test techniques with the specific needs of photonics.

“In the silicon world, our customers like to test as early as possible to initially understand their devices and eventually avoid investing too much into devices that will never work,” said Dan Rishavy, product manager for silicon photonics at FormFactor.

For production testing to really take hold, it will require an ecosystem of testers, handlers, and the other pieces that help to reduce test cost. The ecosystem is just beginning to develop. “We are seeing the first glimmerings of an ecosystem starting to happen,” said Scott Jordan, head of photonics, senior director of nano-automation technologies, and fellow at PI.

Silicon photonics chips need to be stimulated and measured, just like any electrical chip. But electrical probes no longer work, and the mechanisms for getting light into and out of the silicon have required some significant test-equipment development work. That work continues today, but as basic capabilities are established, the focus will move to lowering costs.

From underground transceivers to silicon
Photonics is not new. Early long-haul transceivers were intended to be buried underground for 20 years, so they had to be extremely robust, which meant extremely expensive. That caused a lull in the industry as new applications waited for lower-cost photonics implemented on silicon wafers.

Using silicon for photonics is particularly attractive because designers can leverage all of the infrastructure and ecosystems that already exist for semiconductors. Many of the efficiencies enjoyed by electronic silicon chips can accrue to photonics chips, as well.

However, that infrastructure includes test only to a point. Existing testers can be modified with new test heads to handle the relatively different measurements that will be made, so some of what exists can be used. Yet the practical realities of interfacing with a photonic wafer involve dealing with some very different details. Absent such equipment, engineers have to turn to lab-oriented test equipment, which doesn’t provide the throughput needed for low test costs.

Electrical test of wafers or packaged dies has been developed into a well-optimized flow. While improvements are always possible, what we have today reflects several decades of work to automate test and then reduce the costs associated with testing.

Silicon photonics, in comparison, is far behind. Development of the infrastructure and ecosystems is just getting started. So some of the notions that electrical test engineers may take for granted are still being wrestled with for photonics.

One of the touted benefits of silicon photonics is the ability to mix electrical and photonic circuits on a single die, which would mean testing them both on a single die. While possible, this homogeneous combination isn’t happening for any significant amount of electrical circuitry. Digital logic, in particular, tends to favor aggressive silicon nodes for low cost and high performance. But that silicon is expensive, making low cost possible only due to smaller dies.

Photonics features, in contrast, may be measured in microns rather than nanometers. That means a monolithic implementation would have a small bit of efficient electronics and a huge amount of expensive photonics. “You don’t want to spend what it costs to make a processor at 7nm and throw a huge photonic block right next to it and take up all that real estate,” said FormFactor’s Rishavy.

In reality, electronics and photonics are being put on separate dies, with photonics favoring older process nodes like 130nm. There may be some minor electrical circuits on a photonics chip, but it’s unlikely that any photonics would appear on an aggressive-node electronics chip.

That said, the electrical die is likely to be stacked onto the photonics die and co-packaged. This may be done either while the photonics chips are still in wafer form or after they’ve been reconstituted into a wafer. Testing then can be done at the wafer level for both the electrical and photonic aspects.

Can’t touch this
At a high level, photonics testing should be the same as electrical testing. Signals go in, get processed, and then the outgoing signals are evaluated. But below that level, testing with light is very different from testing with electrons.

Electrical testing involves the simple connection of conductors, whether those are wafer probes or contacts on a final tester. For wafer testing, fixed probe cards are created for each die. The probe card makes contact with all signals at the same time. Delivering and receiving light, on the other hand, isn’t quite so simple.

“This requires very tight alignment of optical probes to couple light into the chip to power up the circuit — and then either read out electrical signals with traditional electrical probes, or couple light out of the chip,” said Twan Korthorst, director of  photonic solutions at Synopsys.

In fact, fibers and waveguides are delicate devices, and touching them would risk damaging them. “Typical ports that you see on these chips are on the order of 10 microns,” said Jordan. “A human hair is 90 microns in diameter. So you can see the problem. It’s very easy to ruin a photonic device.”

Photonics “circuits” (these are different from electrical circuits) need to get light into planar waveguides, and then extract the light somewhere else. It has to be the right light, and it has to be a strong enough signal for the computational components to work properly and to have a strong output signal.

Fig. 1: Two fibers positioned above a photonic wafer. Source: FormFactor

It’s the planar nature of the photonics features that makes this difficult. There are two ways to couple light into a silicon photonics chip. One is through incident light on the surface. “The benefit of silicon photonics is that it is possible to incorporate a grating coupler into the test process that allows vertical access to the optical circuit like an electrical probe,” said Korthorst. It takes light that’s usually in the range of 10° to 12° off vertical, and couples it into the horizontal waveguide.

The other more direct approach is by exposing the waveguide at the edge of the chip, and bringing a fiber to that edge with light around 20° above horizontal. Once a die has been singulated, getting access to the side of the die is, at least conceptually, straightforward. But with an undiced wafer, that edge is not available without some extra work.

Fine positioning adjustments
Another difference from electrical testing is that positioning is more critical. When testing a wafer, an electrical probe can touch down pretty much anywhere on the pad and have a good connection. But when coupling light, the specific angle and position of the fiber (as the source or sink of the light) matter. You can be sloppy and get some light in there, but it won’t be optimal, and it may or may not yield results.

“They need to get the coupling losses under 5dB per facet, if not less than 3dB, in order to get enough of the light into the transceiver to have coherent measurements,” said Rishavy.

The first challenge with designing a photonics probe is that you can’t touch the wafer. You approach it, remaining on the order of a few microns away – the so-called “fly height,” which depends on the coupling grating. This requires a well-calibrated way of positioning the fiber vertically.

But that vertical position isn’t the only positioning consideration. There’s an ideal horizontal spot where the maximum light will enter the waveguide. Anything off that spot will reduce the input – perhaps making it completely ineffective. So x/y positioning is no less important than z positioning. In fact, the angle can also be important, making the three angular degrees of freedom part of the adjustment as well.

A rough indication of x/y position can be extracted from the design files that define the physical chip. “You can bring in a text version of a GDS-II file for your reticle,” said Rishavy. “And it’ll automatically map your RF, your DC, and your optical locations, and then you can set up your test routine to move a motorized positioner through those different locations.” This information is integrated into the test program to get fibers into the general vicinity of where they need to be. But from there, fine adjustment is required to position the fiber tip precisely.

FormFactor approaches this problem using what it calls a “hexapod” affixed with holders for either a fiber or a fiber array. “At the very end, you’ve got the fiber holder that you can change out between single fiber and fiber arrays at varying mechanically machined angles,” said Rishavy. The hexapod can be adjusted with six degrees of freedom – three translational and three rotational – using a piezoelectric actuator. With this, it can scan in a way that is similar to the maximum-power-point tracking (MPPT) done for setting the angle of solar cells.

A “piezoscan” involves simultaneously converging on all the degrees of freedom, cutting what had been an uneconomically long positioning time to a typical two seconds – often less, and occasionally more for, say, a 3D positioning problem. “We can perform a scan very quickly,” said Rishavy. “We scan, say 1,000 points at the input and the output and find the optimal position for that fiber and then move it to that position.”

When positioning the fiber, the many axes of adjustment can prove complicated. The ideal is to position the tip of the fiber where desired, and then be able to make any other angular adjustments. “The hexapod has the ability to set up a ‘pivot point,’ a point of least translation anywhere on its surface,” said Rishavy. “But we need to set the pivot point on the tip of the fiber. So we’ve developed technology where we move the hexapod through a known motion, and we see what happens out at the fiber tip. Then we program the hexapod.”

This and other calibrations are run when fibers or fiber arrays are replaced in their holders (not when repositioning at each new die). “When you change out between different fibers or fiber arrays, you rerun some of the theta [rotational] calibrations,” said Rishavy. “But when someone’s experienced, you’re looking at less than 10 minutes to recalibrate everything and you’re back.”

Fiber arrays are even more difficult. There can be as many as 64 fibers in an array, and they all must line up with their respective gratings. That creates a complex optimization and control problem, which has to be solved in real time. Typical laboratory setups take far too long to do this for production testing. The positioning scan brings this down to an economically viable time.

Measuring the optimal position
But a key question for alignment is, “How do you know when you’re properly aligned?” This involves monitoring the power at an output port. If the input simply drives a waveguide, then the output of that waveguide is the natural port to monitor. But if there is more complex “logic” being performed, like de-multiplexing a signal, then it may not be obvious which output port should be monitored.

“Today’s silicon photonic devices have multiple inputs and outputs, which means it’s not just a matter of lining two things up, because now you have multiple things,” said PI’s Jordan. There may even be cases where, depending on the state of the die, the light may exit no output port.

This raises the question of what, with electrical testing, would be part of a test vector — setting inputs, or following a sequence in such a way that one knows where to look for the output — and ensuring that the state of the system is such that the signal will come out of that output. This process of sensitizing a path to an output, or establishing observability, is well-established for electrical test, but not so much for photonic test.

While it might sound obvious, this is not an automated aspect of photonic test development. Conversations between designer and test engineer may be necessary to set this up, and any such state-setting may be manually implemented in a test program (as opposed to having automatic test-vector generation). Alternatively, if one is sure that the signal will arrive at one or more output ports, the outputs can all be monitored to determine when the highest combined output power has been achieved.

The power may not be the parameter that is optimized during alignment and testing. Jordan suggested a number of parameters that might be used instead. “The customer might want to orient things to optimize polarization. They might want to optimize the extinction ratio. They might want to optimize line width, making it as narrow as possible. There could be various figures of merit that that define how good a device or assembly is.”

One of the ways of testing whether or not the probing and positioning efforts are effective is to look at power repeatability. If you position multiple times, how far off are the signal power measurements? As an example, FormFactor has found its repeatability to be on the order of 0.03 dB. Piezoscan resolution also plays into this. It claims 2nm in a 100×100 nm² range.

One die at a time
One of the implications is that, at present, accurate multi-site testing isn’t practical. “Multi-site is not really possible,” said Rishavy. “In theory, with a 32-channel fiber array, you might be able to reach across to other devices, but I haven’t seen that.” Each site would need to be separately positioned, making for a complicated set of mechanics. As the industry matures, this may become a goal on its own, but it’s not a strong area of development for now.

In FormFactor’s situation, one can use up to three hexapods at a time, approaching the die from the east, west, and south. Movable RF probes can replace the hexapods if desired. All the hexapods and RF probes can be aligned in parallel to keep setup time down.

A standard electrical probe card also can be worked into the setup, as well, for doing both electrical and photonic testing with one setup. “The electrical probes make contact as you as you put the chuck in the contact position, but your fibers are still sitting above it, and then you’ll do the optical optimization after your electrical contacts are in place,” explained Rishavy.

Fig. 2: A typical test setup with two hexapods and a downward-facing camera. Source: FormFactor

One unusual aspect of photonics testing is that a reticle may have many individual components in it. In FormFactor’s case, the wafer chuck can be positioned once for a reticle, with the hexapods then positioning themselves for each die within the reticle.

Coming from the edge
Accessing the waveguide via the die edge is trickier on a wafer. “What some companies are doing is to etch a trench along the street of the wafer around 200 microns deep,” explained Rishavy. “And then that’ll expose that edge facet. You come in at 20 degrees off horizontal into that trench, get it as close as possible to that edge facet, both at the input and the output, and then shine light through and make your measurement.”

Fig. 3: A tapered-lens fiber accessing a port from the side using an etched trench. Source: FormFactor

Overall, testing an entire wafer can be slow, even with fast alignment on each die. “It can be hours per wafer,” said Rishavy. There is the roughly 10-minute calibration step done at setup and whenever a fiber or fiber array is traded out. Beyond that, it’s all positioning (at less than 2 seconds per position) and actual testing – with a huge number of potential sites on a wafer.

It also may be necessary to inspect fiber tips occasionally for dirt or damage. They can be checked using an additional horizontal camera in the setup or having a mirror off to the side of the test head that lets an existing downward-facing camera view the tip. “If you’re having some measurement problems, you can see, ‘Is it my fiber that’s causing the problem or is it damaged? Did I accidentally hit it on something, or is it full of dust, or did it pick up particles or whatever?” explained Rishavy. This setup can also be used to calibrate the distance from the edge to the first fiber of a fiber array.

Fig. 4: Auxiliary tools for calibrating Z-height and optical positioning, measuring fiber power, inspecting fiber tips, measuring edge-to-first-fiber distance of fiber arrays, and testing singulated dies. Source: Adapted from a FormFactor image

Continued development focuses on solutions for full-range temperature testing. “We have customers who want to test from -40°C up to 125°C,” said Rishavy.

Assembly and final test
Once wafers are diced, the dies can be packaged. Because processing such dies is currently relatively expensive, and because damage is possible during assembly, some assembly machines can perform a quick live/dead test. This merely confirms whether it’s worth continuing to process the unit. “It’s very simple testing – nothing like what’s done in a wafer prober,” said Jordan. “But it suffices to tell them, ‘Have I killed this chip yet? Or can it go on for additional packaging steps?’”

Then, a “final test” can be performed. And here again, there’s not a well-established ecosystem of testers, test heads, and handlers to run high volumes. For example, connecting fibers for testing may involve an operator manually plugging fibers from the tester into the ports on the unit. Jordan noted that robotics exist for plugging fibers into panels for networking, so it may be possible to adapt such technology for testers. But that appears to remain as future work.

Photonics producers, meanwhile, now are trying to capture as much sellable material as possible. “We have seen some players start to do binning,” said Jordan. Bins can be established based on photonic and/or electrical parameters. While this is an old practice for electrical test, it’s leading edge for silicon photonics.

These challenges for light-based chips may extend beyond photonics waveguides. Advantest pointed to microLEDs as having similar characteristics. “Although conceptually simpler, manufacturing microLEDs is not without challenges,” said Kotaro Hasegawa, functional manager, Gunma R&D center at Advantest. With the potential to replace larger LEDs and OLEDs, microLEDs could be produced in very high volumes – but they would need very low costs.

Advantest is working on ways to run tests in parallel to ensure favorable economics. “One possible answer is a massively parallel dual optical-electrical test cell with extremely fast test performance that meets both the test and cost requirements,” Hasegawa continued.

Once these basic silicon photonics capabilities are well established, then focus will move to reducing costs to help improve the economic value that they provide. There is plenty of opportunity for creative development in this space.