The Week In Review: Design

Synopsys buys SerDes IP firm, integrates tools in RTL-to-GDSII flow; IP security; hybrid memory systems.


Synopsys acquired Silicon and Beyond, a provider of high-speed SerDes and ADC/DAC IP. The company was founded in 2012 as SilabTech and headquartered in Bangalore. Synopsys highlighted the team of R&D engineers with high-speed SerDes expertise that would be joining with the acquisition. Terms of the deal were not disclosed.

ANSYS will acquire OPTIS, a provider of software for scientific simulation of light, human vision and physics-based visualization. Headquartered in La Farlède, France, OPTIS was founded in 1989. ANSYS expects the acquisition to result in a comprehensive sensor solution for the automotive market, covering visible and infrared light, electromagnetics and acoustics for camera, radar and lidar. The deal is expected to close in the second quarter of 2018. Terms were not disclosed.

Synopsys debuted its Fusion technology, aiming for better integration of optimization and signoff analysis. Synopsys argues that the boundaries between synthesis, place-and-route, and signoff functions in a traditional RTL-to-GDSII design flow cause rework when transitioning from one design phase to the next and leads to degraded full-flow TTR and unmet PPA targets.

Fusion provides single data model for both logical and physical representation. Some focuses include common engines between synthesis and place-and-route, plus moving synthesis optimization technology into place-and-route and place-and-route optimization technology into synthesis; signoff analysis inside implementation, to improve flow predictability; using the golden signoff backbone for both optimization and signoff; and a combination of design-for-test RTL analysis and design-for-test synthesis integrated into implementation.

Additionally, Synopsys teamed up with ANSYS to integrate RedHawk Analysis Fusion as a complete in-design power integrity add-on solution for Synopsys IC Compiler II place-and-route system users. It will allow place-and-route engineers to perform early power grid integrity checks, as well as static and dynamic power analysis at multiple points in the design flow.

Synopsys’ design flows for digital RTL through signoff, custom/AMS, and library development have been certified for ISO 26262 compliance by exida, allowing Synopsys tools and flows to be deployed in the development of automotive designs with safety requirements from ASIL A through ASIL D. Functional safety kits are available for download.

Cadence’s Sigrity PowerDC technology now supports Future Facilities’ new open neutral file format, with the goal of sharing design models between different thermal/mechanical simulation toolsets.

Accellera will explore standardizing security assurance requirements for IP with a new Proposed Working Group. The group will assess whether there’s interest and feasibility in defining an automated systematic approach to integrating security assurance collateral. “Currently there is no single standard to address security assurance in the development and delivery of IP to silicon integrators,” said Martin Barnasconi, Accellera Technical Committee Chair. The first meeting will be held Tuesday, April 17 from 10am – noon PT at Intel SC12 in Santa Clara, CA.

IEEE published a new amendment to the 802.3 standard, 802.3cc-2017—Standard for Ethernet Amendment: Physical Layer and Management Parameters for Serial 25 Gb/s Ethernet Operation Over Single-Mode Fiber. It defines single-lane 25 Gb/s PHYs for operation over single-mode fiber with lengths up to 10 km and 40 km to better support metropolitan networks.

Rambus and IBM are teaming up to research hybrid memory systems for future data centers. The goal is to create a high-capacity memory subsystem that delivers comparable performance to DRAM alone. Rambus will develop a flexible prototype hybrid memory platform using the OpenCAPI interface to demonstrate performance of multiple memory types in real-world server applications.

Renesas adopted Synopsys‘ Design Platform for development of its R-Car V3H SoC designed for smart cameras in Level 3 and Level 4 autonomous vehicles. The R-Car V3H SoC includes a new, highly power-efficient hardware accelerator for high-performance CNNs.

Rambus inked a patent license agreement with Beijing Tongfang Microelectronics, a fabless chip design company focusing on smart cards and related technologies, including access to Rambus’ DPA Countermeasures portfolio.

2018 CEO Outlook: Apr. 5, 5:30 p.m. – 8:30 p.m. in San Jose, CA. This panel, hosted by the ESD Alliance, will bring together CEOs Dean Drako of IC Manage, Grant Pierce of Sonics, Wally Rhines of Mentor, and Simon Segars of Arm for their views of the major trends and opportunities in the semiconductor design ecosystem, including an interactive, moderated audience discussion.

D&R IP-SoC Day: Apr. 5 in Santa Clara, CA. The one-day event will discuss trends in IP including AI and deep learning architectures, RISC-V, eFPGAs, and IP management and reuse.

All You Need to Know About Inbound Digital Marketing: Apr. 26 in Milpitas, CA. The ESD Alliance will host a workshop focused on new marketing strategies and techniques for EDA, IP, and services companies. Nicolas Athanasopoulos, OneSpin’s Head of Digital Strategy and Dave Kelf, Chief Marketing Officer at Breker Verification Systems will lead the workshop.

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