The Week In Review: Design

ESD Alliance joins SEMI; desktop prototyping; timing optimization; securing IoT, processors.


The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of both organizations.

Synopsys launched a new desktop form factor of its HAPS-80 prototyping system. Targeted at mid-range SoC prototyping, HAPS-80D has built-in infrastructure to support GPIO, UARTs and a variety of SoC peripherals. It includes debug infrastructure for HAPS GSV with support for Synopsys’ SoC debug platform, as well as direct connection to a software debugger.

Teklatech introduced bulk timing optimization capabilities at the pre-clock tree synthesis stage to its FloorDirector platform for dynamic power integrity analysis. FloorDirector-BTO supports multi-dimensional optimization objectives and constraints: Reduce TNS (both setup and hold) and Number of Failing Endpoints (NFE), or put focus on near failing endpoints. Targets, constraints and trade-offs can be adjusted through user controlled parameters. It is available as a standalone tool.

Arm debuted a SoC framework aimed at development of secure IoT nodes, gateways, and embedded applications. The SDK-700 System Design Kit has a flexible compute architecture combining Cortex-A and Cortex-M processors and includes pre-built security IP such as firewalls, secure enclave, and TrustZone. The framework is designed as a foundation for Azure Sphere, Microsoft’s IoT MCU security program.

Rambus uncorked CryptoManager Root of Trust, a fully programmable hardware security core built with a custom RISC-V CPU. Intended to mitigate the risk of vulnerabilities like Meltdown and Spectre, its processing core creates a siloed architecture that isolates and secures the execution of sensitive code, processes and algorithms from the primary processor. It targets a range of applications including networking, automotive, and IoT.

Synopsys signed a multi-year subscription agreement with Arm, giving the company early access to a range of Arm’s IP for the purpose of optimizing tools and design flows for Arm-based SoCs. A series of workshops is planned that focus on implementation and verification of Arm IP with Synopsys tools.

HPE, Arm, and SUSE are teaming up on a program to establish supercomputer deployments at three UK universities (Bristol, Leicester, and Edinburgh) to spur early adoption of Arm for high-performance computing in the UK.

IEEE published a standard revision to IEEE 1800, also known as SystemVerilog. This revision addresses inconsistencies and corrects discovered errata based on feedback from users working with complex ICs. The standard is available at no cost through the Accellera-sponsored IEEE Get Program.

Si2 is seeking participants for an international survey to identify ways to streamline and improve the IC design ecosystem along with specific ways the industry can manage the rising costs of more complex designs and smaller geometries. Survey results will be announced in a DAC 2018 white paper.

All You Need to Know About Inbound Digital Marketing: Apr. 26 in Milpitas, CA. The ESD Alliance will host a workshop focused on new marketing strategies and techniques for EDA, IP, and services companies. Nicolas Athanasopoulos, OneSpin’s Head of Digital Strategy and Dave Kelf, Chief Marketing Officer at Breker Verification Systems will lead the workshop.

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