Time To Look At SOI Again

Chipmakers have the luxury of looking at several process options when developing chips at the 28nm node and beyond.

Using bulk CMOS, for example, chipmakers can scale planar transistors down to 20nm. Then, at 20nm, planar runs out of gas due to the so-called short-channel effect. At that point, IC makers must migrate towards finFETs at 16nm/14nm and beyond.

Another process option is fully-depleted silicon-on-insulator (FDSOI) technology, which has been in the market for several years. To date, however, FDSOI remains a niche and is still trying to gain widespread adoption. In fact, a large percentage of designs are using bulk CMOS today. As before, IBM and STMicroelectronics are among the few chipmakers using FDSOI.

FDSOI uses an ultra-thin layer of silicon over a buried oxide as a means to reduce leakage and variation. FDSOI also boasts a back-bias feature. One knock on FDSOI is the cost. SOI substrates are more expensive than bulk CMOS wafers.

Now, however, it might be time to take another look at FDSOI. In recent times, there have been some significant moves in the arena, providing chipmakers with new options. Earlier this year, for example, Samsung announced plans to provide foundry services for 28nm FDSOI technology.

More recently, the SOI industry has revised its FDSOI roadmap. Previously, the industry planned to extend planar FDSOI for three generations from 28nm, to 14nm, and then to 10nm. 20nm FDSOI was not on the industry’s roadmap. Then, the industry would offer finFETs on SOI at 7nm.

Now, the industry is developing a 20nm FDSOI process after all. And IBM plans to field finFETs on SOI at 14nm and/or 10nm. In other words, the SOI industry is expanding, if not accelerating, its roadmap.

GlobalFoundries, for one, plans to field a 20nm FDSOI process in 2015, according to Mike Mendicino, senior director of product management at the silicon foundry provider. GlobalFoundries is also a foundry for 28nm FDSOI. “We’re seeing a lot of interest from customers (for FDSOI),” he said. “There is still a place for FDSOI in the market.”

Still, the most compelling market for FDSOI resides at the 28nm node. 28nm is expected to be a long-running node. But still, the bulk CMOS camp won’t give up the 28nm market so easily. TSMC, for example, recently expanded its process lineup with a new and cheap 28nm bulk CMOS derivative. In addition, TSMC just rolled out a new ultra-low power process for its 55nm, 40nm and 28nm nodes.

On the finFET front, meanwhile, Intel is shipping its second-generation finFET technology based on a 14nm process and bulk CMOS. The other foundries are readying their initial 16nm/14nm finFETs, also based on bulk. Intel, as well as the foundries, have dismissed SOI in favor of bulk.

Intel’s 14nm process was late by about six months due to yield issues. And the other foundries are currently struggling with an assortment of issues with their bulk-based finFETs at 16nm/14nm. And the challenges are expected to increase at the 10nm node and beyond.

So for finFETs, it might be time to take a hard look at SOI again. At the recent IEEE S3S Conference, IBM described an SOI finFET technology at 10nm, which is said to be a more simple process than bulk finFETs. “Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice,” said Terence Hook, a senior technical staff member at IBM, in a paper. “Once a wafer with the desired thickness is available, formation of the fin is blindingly simple. In contrast, forming a fin of a desired dimension in a bulk substrate requires at least three additional steps of fill, polish, and etch. Although significant progress has been made in improving the control of the bulk process, the fundamental control capability in bulk is still three times worse than SOI.”

Of course, there are a multitude of trade-offs between bulk versus SOI finFETs. SOI suffers from potential cost and ecosystem issues. “Two potential concerns for SOI-based finFETs have been the effect of self-heating and a shortfall in the ability to exert strain on the channel from the source/drain region,” Hook said. “While both of these aspects may be of some interest at the 10nm node, the future direction of technology renders these issues moot – not so much because SOI finFETs will be less susceptible to these concerns, but rather because bulk devices will become more so.”

What’s the bottom line here? Chipmakers, who may have rejected a particular technology option before, should keep an open mind going forward. It never hurts to explore all options in a challenging market.