Tradeoffs On The Fly

By Ann Steffora Mutschler
With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage.

“To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectronics. “From the technology point of view the solution is fully depleted devices. We have two ways to obtain those fully depleted devices. One is staying planar through an SOI with a thin silicon substrate. The other is 3D—the finFET, or TriGate as Intel is calling it.”

While Intel is going with the TriGate approach, ST has chosen the fully-depleted silicon on insulator (FD-SOI) technology and has been working for many years in close cooperation with the CEA-Leti Research Center and with Soitec, which is working on the silicon substrates on SOI technology, he noted. Further, Cesano said, “there was a Fellow here, an expert in technology here in Crolles that 15 years ago started developing these concepts about having those very thin silicon films over thin boxes. At the time it was a concept; it was not manufacturable. There was not the technology to do it and also, frankly speaking, the technologies that were available at that time were more than enough to fulfill the customer’s needs so there was not the need to go to those extreme solutions.”

Fast forward to today and ST realized this was an exceptional solution to overcome the limits of bulk planar technology and obtain fully depleted devices that are still shrinkable, he said. Last month, STMicroelectronics said its 28nm FD-SOI technology platform was open for pre-production from its Crolles 300mm manufacturing facility and the company is already developing the 14nm node.

From speaking with semiconductor companies, Andy Inness, place and route product specialist at Mentor, observed that FD-SOI is actually proving to be more helpful than finFETs. Moreover, both FD-SOI and finFETs can be combined, so the isolation from FD-SOI helps reduce variability and improve performance because it gives more predictability as to how the wells are going to operate.

“It’s more isolated and therefore more predictable with less transient currents, less leakage currents—all those kinds of things,” Inness said. “You get better performance and more predictability even if it costs you a little bit in manufacturing. Compared to finFET, we’ve seen with at least a couple customers that FD-SOI seems to be the one they are gravitating towards first because from an EDA perspective, from a place and route perspective, it’s almost transparent. You can almost just map the GDS and plug in different library cells that are the same footprint, same everything, but still gain the performance and/or the power benefits from it.”

Steve Longoria, senior vice president of worldwide strategic business development at Soitec agreed. “The big advantage of fully depleted SOI is that you can still use the same design flow with a different SPICE model that has better characteristics and you get a better transistor. It’s no more complex than moving from 65nm to 45nm, and it’s a good interim step—FD-SOI at 28 nm and finFETs at 14nm.”

But developing chips at 20nm and 14nm will require at least double patterning, and in some cases multi-patterning. That has prompted many industry executives to say that 28nm will be around longer than most process nodes, particularly with the added benefit of FD-SOI. STMicroelectronics, for one, has committed to that scheme, rolling out FD-SOI test chips at that node which it claims produce similar gains to moving to finFETs.

Longoria says the benefit of moving to FD-SOI can be at least 25% to 30% improvement in power or performance. ST is claiming significantly higher benefits with the addition of back biasing to dynamically trade off power and performance.

“The reality is that 40nm is mainstream for most companies, not 20nm,” he said. “The next step is to tape out at 28nm, and there is a power/performance advantage by moving to fully depleted SOI rather than bulk at 28nm or even 20nm.”

In addition, some companies are looking at combining both FD-SOI and finFETs. IBM, for one, plans to add finFETs on FD-SOI at some future node, according to Gary Patton, vice president of the IBM Semiconductor Research and Development Center. Sources say the node in question is 10nm.

big.LITTLE versus FD-SOI
Everywhere you turn today, ARM’s cores and architectures are pervasive, but it also begs the question as to whether there are other approaches to achieve the same end result in terms of the power and performance tradeoffs. Instead of looking at it from the architecture side, ST would suggest looking at it from the process side. Dynamic body biasing allows for these tradeoffs to be made.

Body biasing already existed in bulk planar technologies but it was not very effective, Cesano said. “The effectiveness of the body biasing in an old technology is roughly 25 millivolts per volt. That means I apply one volt on the backside—so I apply some body biasing and I can lower or increase the Vt, the threshold voltage of my device, by 25 mV, which is not that much. If I pass the supply of the diode, which is between the wells, I have a problem because if I pass the classical diode junction voltage, the diode starts conducting. That means that I cannot polarize the wells more than 300 mV for each well; otherwise, I will have some current that starts flowing because I have a diode between the wells. So not only I have a biasing voltage, which is not very effective, but also I am limited by those diodes about the maximum Vdd that I can apply for the biasing.”

The classical usage done in the past was process compensation, but with FD-SOI, “this is much, much better because the effectiveness of the biasing is 85 mV per volt.  Not only that, but we don’t have any more the problem of leakage currents or diodes through the well so in reality we can apply biasing up to 2.5volts. That means that I can control my Vt of 160-200 millivolts, which is huge,” he said.

From an architectural point of view this is something companies such as ARM are trying to mimic with a different solution. “If you take, for example, the implementation of the big.LITTLE, which is proposed by ARM, it’s a way to say I have the big processor for the huge task which is there for the heavy duty, I have a small processor which is optimized for the leakage, and then I switch between the two depending on what I have to do,” Cesano said.

He pointed out that this approach has some drawbacks because on one side it takes more area, which means that you cannot have one core that is capable of being optimized both for the heavy duty and the lightweight jobs. On the other side you need to implement both and to put both on silicon. The other problem is the job scheduler has to decide in an asymmetrical architecture what has to be allocated to the heavy duty core and what has to be allocated on the light core.

“On our side with the biasing it’s much simpler because somehow the job is always allocated on the core that is available, and as you control the DVFS for dynamically scaling the voltage and frequency in our case we scale two voltages. One is the main voltage and the second one is the bias voltage. What we have is the DVFS with two supplies instead of one,” Cesano said.