Uncertainty Increases About What’s Next

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding.

But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicated to resolve and even more expensive. In fact, collectively they make it hard to do basic things like come up with a cohesive design, perform place and route, verify that it all works and manufacture it with sufficient yield. Discussions have moved in verification circles from total coverage to optimal coverage, where not everything has to work to perfection.

Even architectural approaches are up in the air. The cost of equipping fabs for 450mm wafers at 10nm is tens of billions of dollars—the exact costs are still theoretical. Add in EUV and multipatterning, and the cost of using this
advanced equipment becomes daunting, particularly if it isn’t being used for the same number of wafers per hour.

This has led to a refocusing on new approaches, such as fan outs—basically the equivalent of a PCB in a package—which is gaining renewed attention, along with 2.5D and 3D stacked die. Continuing to shrink features, while not in danger of hitting a technological wall, is certainly approaching an economic wall. Rather than hard numbers, return on investment is becoming a formula based on a lot of “what ifs.”

“The whole industry is frightened by NRE changes,” said Jack Harding, president and CEO of eSilicon. “At 28nm, the layout, third-party IP and mask sets cost $7 million to $10 million in NRE. At 20nm, you can expect that number to increase 20% to 25%. And at 14/16nm with finFETs, you’re talking more than $15 million in NRE. There is a shrinking number of people who can afford to pull the trigger. On top of that, we have process technology changes and 450mm, so the number of chips companies can afford to make is dropping precipitously. They may make one or two chips a year.”

Stacking die is an option, but it also requires some significant realignment inside of companies. The problem is similar to the one faced by IT departments back in the early 2000s, when the number of servers ballooned because IT managers saw it as a cheap investment for boosting performance. The IT managers didn’t own the operational expense budget, though. That was handled by an entirely different department. It wasn’t until both budgets came under the control of the CIO that companies began thinking about how to use resources more efficiently.

A similar silo effect is occurring today in the chip design world. NRE is part of the R&D budget, but the unit cost is owned on the operations side. It will take a top-down reorganization to overcome that barrier, just as it did for the IT departments.

“This needs to reach the CEO to sort it all out,” said Harding.

If you build it, what will it look like?
On a fundamental chip design level, there are even questions about what to make. Tom Quan, director at TSMC, said there is growing interest in fan-out approaches—basically one step before 2.5D where components are fanned out around a chip but in the same package.

“You’ve got things like inductors and capacitors outside the chip, and because they’re outside the quality can be better,” Quan said. “But they’re also not on the board. And we already have all the materials and we know how to do it. So this can help to decrease the number of Dcaps, which reduces the cost, but the size is larger for the package.”

There also is more of a focus on sharing components as a way of reducing costs and cutting development time.

“Particularly for things that are not battery operated, you don’t want to design the whole chip from scratch,” said Kurt Shuler, vice president of marketing at Arteris. “So you take the chip, combine it with an I/O chip, and that’s sold as a solution. We’ve seen a couple customers doing that. The same is happening with MIPI LLI (low-latency interface) and C2C (chip-to-chip) connections, which share memory. People are using it in cars, networking technology and home gateways.”

Software, in this case, can take care of the scheduling between components, meaning it can be optimized separately to ensure there are no unexpected costs.

Redefining progress
But along with this kind of architectural shift and sharing of components, there are deeper questions about what exactly has to move forward to the next process node. The most advanced processes may be required for only part of the chip. Even the foundries are recognizing that concern, which is why both TSMC and GlobalFoundries have been actively developing interposers for 2.5D stacking, and why there has been so much industry-sponsored research on through-silicon vias, thinned-wafer handling, packaging and test.

“You do have to understand why you are switching to the next node,” said Frank Schirrmeister, group director of product marketing for the System Development System & Software Realization Group at Cadence. “We’re not seeing a single inflection point, but we are seeing people asking questions about what kind of programmability they need. And they’re asking whether the programmability is needed in hardware or software with ARM cores. This isn’t an inflection of one that that doesn’t work.”

Schirrmeister said the shifts underway appear to be favoring platforms, with more differentiation around the edges. But he noted this is good for EDA because it’s incremental business with a very long tail. So rather than eroding existing tools business, it’s creating demand for new tools in places they were never used before.

That observation is being echoed across the semiconductor industry, particularly in the IP world where the management of IP is beginning to gain serious traction—even in the analog/mixed signal side, which is meeting the biggest resistance to moving to the most advanced process nodes.

“We’re seeing a pickup for data management and IP management on that side,” said Karim Khalfan, technical marketing manager at Cliosoft. “There are a few companies that have deployed it already for analog-mixed signal. The digital world is more used to managing IP.”

In the analog and RF world, engineers are still working with schematic diagrams. But as this shift occurs, they are beginning to adopt new tools. How fast this will progress, and how widespread this shift will become is anyone’s guess. But it does indicate a willingness to explore new options after decades of simply shrinking features every couple years.