Week In Review: Design, Low Power

M&A
Intel will acquire fabless company eASIC. Founded in 1999, eASIC sells structured ASIC platforms that act as a midpoint between FPGAs and standard cell ASICs by combining FPGA-like logic and design flows with single via routing. Eventually, Intel sees potential in using its Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution, said Dan McNamara, corporate vice president and general manager of Intel’s Programmable Solutions Group. eASIC will become part of that group, which was formed when Intel acquired Altera. The deal is expected to close in the third quarter of 2018. Terms were not disclosed.

Tools
Helic unveiled a new tool for electromagnetic crosstalk risk analysis. Pharos combines a high-capacity EM extraction engine with high-performance simulation technology to provide a prioritized list of potential EM crosstalk aggressors per victim net and highlight nets susceptible to EM crosstalk.

AMIQ EDA’s Design and Verification Tools (DVT) Eclipse IDE now supports Portable Test and Stimulus Standard 1.0. Features for PSS include on-the-fly compilation and error detection with quick-fix proposals, hyperlinks to jump to declarations and usages, context sensitive auto-completion of PSS constructs, structural views for browsing type and component hierarchies, project database queries, diagrams, rename refactoring, and source code formatting.

Synopsys and the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS) announced that a new, production-ready silicon photonics process design kit (PDK) based on IMECAS’ 8-inch CMOS process is now available in the Synopsys PhoeniX OptoDesigner photonic integrated circuit layout software. The IMECAS PDK gives access to passive photonic components optimized for the 1550nm communications wavelength, including several versions of single-mode waveguides, grating couplers, MMIs, waveguide crossings, and thermo-optic heaters used for light modulation.

Deals
Mobileye purchased multiple licenses of Arteris IP Ncore Cache Coherent Interconnect, FlexNoC Interconnect, and the Ncore and FlexNoC Resilience Packages for functional safety and AI hardware acceleration, which will provide the on-chip communications backbone of Mobileye’s next-generation ISO 26262 ASIL B(D) capable EyeQ SoCs.

ArcSoft ported beauty shot, high dynamic range (HDR), bokeh and facial unlock applications to Cadence’s Vision P6 DSP. The joint solution has been designed into an applications processor from a leading global provider and is now shipping in smartphones.

Biometric devices maker Goodix adopted Helic’s electromagnetic-aware flow and tools as part of its mixed signal design environment.

Tool qualification reports for Mentor’s Calibre physical verification tools have been certified for ISO 26262 by independent testing company SGS-TÜV Saar. The reports are qualified for use in any safety-critical ISO 26262 designs and verification flows at all criticality levels up to and including ASIL D, regardless of the design house or manufacturing site.

Markets
What’s the state of the engineering profession and workforce? A survey by IEEE GlobalSpec finds that 53% of engineers say they are required to do more with less, and 40% warn that pressure to meet deadlines is putting product quality/rework at risk. A large number of engineers are also reaching retirement age, leaving an experience gap even as a majority say a lack of specialized knowledge is jeopardizing their company’s productivity.

Revenue from AI chips is expected to grow rapidly in the next decade, according to market research firm MarketsandMarkets. “The AI chipsets market was valued for $5.2 billion in 2017 and is expected to reach $59.26 billion by 2025, at a CAGR of 35.5% between 2018 and 2025,” said Sachin Garg, Associate Director at MarketsandMarkets. Chips for machine learning, in particular, are projected to achieve 37.2% CAGR between 2018 and 2025, with a market size exceeding $30 billion.