Week In Review: Design, Low Power

SMIT acquires S2C; RTL-to-GDSII, mixed-signal, synthesis tools; RISC-V simulator.


SMIT Holdings acquired S2C, a provider of FPGA prototyping hardware and software as well as interfaces and accessories, for $19 million, plus up to US$2 million in milestone based payments to the key management team. S2C was founded in 2003. SMIT, based in Hong Kong, makes pay TV broadcasting access and mobile point-of-sale payment systems for the Chinese market.

Tools & IP
Synopsys released a new RTL-to-GDSII product, Fusion Complier, that incorporates high-capacity synthesis technology with IC Compiler II place-and-route technology. It is built on a single, highly-scalable data model that supports common signoff analysis, optimization, concurrent clock data optimization, clock topology creation, and routing engines. Toshiba, Samsung SARC and ACL, and Socionext noted having adopted the tool.

Mentor launched a new mixed-signal platform that combines its Analog FastSPICE circuit simulator with industry-standard HDL simulators for verification of complex nanometer-scale mixed-signal ICs. The Symphony platform provides nanometer-scale SPICE accuracy and allows users to remain in their existing use model and existing verification infrastructure. It provides connectivity and functionality checks, as well as mixed-signal IP characterization across A/D subsystems. IDT and Semtech noted adopting the tool.

Synopsys also announced the latest version of its RTL synthesis product, Design Compiler NXT. New optimizations include power-driven mapping and structuring techniques, Concurrent Clock and Data (CCD) optimization, and a new approach to distributed synthesis. The tool shares a common library and advanced placement technologies with IC Compiler II, in addition to aligned RC, net topology, and density modeling. Renesas noted adopting the tool.

Imperas released RISC-V Open Virtual Platform Simulator, a free RISC-V simulator and model of a complete single-core RISC-V CPU aimed at jump starting software development. The instruction-accurate model and simulator covers all the RISC-V permitted configurations and variants. It is available for download now.

OpenMP API 5.0 has been released. The specification defines a set of compiler directives, library routines, and environment variables that can be used to specify high-level parallelism. The latest version focuses on adding full support for accelerator devices, and now covers the entire hardware spectrum from embedded and accelerators to multicore systems with shared-memory. Debugging and performance analysis is also improved, it now supports multilevel memory systems and a fully descriptive loop construct.

Vidatronic uncorked a line of voltage and current reference IP cores in the TSMC 130nm process. The IP cores are optimized for low power ASSP and PMIC integration. They do not require any external components in order to operate and offer the option of integration of the temperature sensor and current reference with the voltage reference into a single IP block.

Infinera Corp.’s process design kit (PDK) is now available for Synopsys’ OptSim Circuit tool. It allows users to schematically capture, simulate, and verify indium phosphide (InP)-based photonic integrated circuit (PIC) designs with Infinera’s PDK building blocks, and then send the completed circuit design to Infinera for physical implementation, verification, and fabrication using Infinera’s InP PIC process.

A PDK based on Advanced Micro Foundry’s silicon photonics process is also available in Synopsys’ OptoDesigner photonic layout software. The AMF PDK includes passive and active photonic components optimized for 1550 and 1310 nm communications wavelengths, including high-speed modulators, low loss couplers, polarization components, and high-bandwidth photo detectors.

Ansys reported third quarter financial results for 2018 with revenue of $289.4 million. On a GAAP basis, earnings per share were $1.04, while non-GAAP earnings were $1.31 per share. The company changed accounting standards this year; under the previous rules, revenue was $302.0 million in Q3 2018, up 10% from the same quarter last year. GAAP earnings per share were $1.16, up 36% from $0.85 in Q3 2017, and non-GAAP earnings per share were $1.46, up 39% from $1.05 per share. Ansys raised its guidance for the year, expecting revenue in the range of $1.23 – $1.25 million.

John Zhuang was named the new CEO of Brite Semiconductor. Zhuang joined the company in 2013 and has been the acting CEO since September. He held positions at Texas Instruments, Conexant, SimpleTech and Broadcom and co-founded Novel Data Solutions Corporation. Along with ASIC design services targeting SMIC processes, Brite provides DDR controller and PHY IP.

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