Week In Review: Design, Low Power

Arm mobile platform; making software for RISC-V; GPU AI supercomputer; scaling up batteries.


Arm debuted its latest platform for mobile computing. Arm Total Compute Solutions 2023 adds the new Immortalis-G720 GPU based on the 5th Generation GPU architecture, which redefines parts of the graphics pipeline to reduce memory bandwidth for the next generation of high geometry games and real-time 3D applications. The company also added two new Mali GPUs. In addition, Arm introduced a cluster of Armv9 CPUs, which it claims offers double-digit performance gains alongside significant efficiency improvements. CPU introductions include the high-performance Cortex-X4, which was taped out on the TSMC N3E process, as well as new big and LITTLE cores in the Arm Cortex-A720 and Cortex-A520. The lineup also includes a new DynamIQ Shared Unit, DSU-120, which is designed for demanding multi-thread use cases. Cadence and Synopsys introduced tool and IP solutions optimized for Arm’s latest offerings, along with adoption and implementation kits.

Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve observability of chiplets over time, something that is particularly important as these devices are used in safety-critical and mission-critical applications.

Renesas Electronics debuted three new MCU groups targeting motor control applications. New products in the RA family of Arm Cortex-M devices offer 100MHz or 200MHz with up to 256KB of flash and 40KB SRAM, along with trigonometric function units (TFUs) for acceleration, advanced ADC with integrated PGA, and communication interfaces including CAN FD. The new RX family devices operate at 120 MHz with up to 512KB of flash memory and 64KB SRAM and provide TFUs, on-chip timing, and interrupt control.

Keysight Technologies debuted a lidar target simulator that can simulate test targets at defined distance and reflectivity for validation of automotive lidar sensors.

Infineon Technologies extended its AURIX TC3xx MCAL by adding ASIL D and SIL-2 compliant drivers to support AUTOSARv4.4.0 and facilitate software development for OEMs.

Imagination Technologies uncorked a new lineup of GPUs with native support for HDR for cost-sensitive consumer devices such as wearables, smart home hubs, set-top boxes, and DTVs.

Magnachip is planning to separate its display and power businesses into separate operating entities. The new display business will remain a wholly owned subsidiary.

SiNBLE Technology launched to provide IC and subsystem design implementation services.

Industry executives explore the challenges and opportunities involving heterogeneous integration, geopolitics, and AI.

The UK Battery Industrialisation Centre (UKBIC) will set up a new £36 million (~$44.5 million) Flexible Industrialisation Line (FIL) for battery cell manufacturing and testing. FIL aims to bridge the gap between proof-of-concept and pilot lines run by the University of Warwick’s Manufacturing Group (which will jointly run the new line) and UKBIC’s volume line, which provides a range of tools to help companies develop large-scale manufacturing processes for new electrodes, battery cells, module and pack structures. “UKBIC’s existing Volume Industrialisation Line is ideally placed for the later stages of manufacturing process to validate that product can be made in volumes of tens of thousands and above. This is where it becomes cost-effective and representative of an industrial plant run, and therefore a vital part of the commercialization process. The gap for the UK is in early production quantities, between the low hundreds and low thousands of cells, which is where our new line will come in,” said Tony Harper, director of the UK’s Faraday Battery Challenge. Funding for the new line comes from UK Research and Innovation.


The RISC-V Software Ecosystem (RISE) Project launched to accelerate the availability of software for high-performance and power-efficient RISC-V cores running high level operating systems for a variety of market segments. It will focus on establishing a software ecosystem specifically for application processors that includes software development tools, virtualization support, language runtimes, Linux distribution integration, and system firmware, working upstream first with existing open source communities in accordance with open source best practices.

The IP industry is undergoing several transformations that will make it difficult for new companies to enter the market, and more expensive for those that remain. As the industry migrates to the next level of complexity with chiplets, even more models, deliverables, and collateral will be required, especially as the IP and chiplets become more opaque. They almost certainly will be required to have manufactured those chiplets and make them available for evaluation, which also will require design of some form of substrate or interposer.

Semidynamics uncorked a customizable Vector Unit for its 64-bit RISC-V cores. It can be adjusted to support different data types with a configurable number of vector cores and number of bits of each vector register depending on target application.

SiFive gave its WorldGuard security model to RISC-V International. WorldGuard is a hardware-enhanced software isolation solution to provide protection against improper access to memory or devices by software applications and other bus initiators.

Andes Technology proposed its AndeSentry platform as a collaborative framework through which companies within the RISC-V ecosystem can work together to enhance RISC-V solutions security against a wide range of threats, including both cyber and physical attacks.


Siemens Digital Industries Software teamed up with Siliconware Precision Industries Co., Ltd. to develop and implement a new IC package assembly planning and 3D layout vs. schematic (LVS) assembly verification workflow for SPIL’s fan-out family of advanced IC packaging technologies.

MIPS will use Siemens’ Veloce proFPGA platform to demonstrate MIPS’ IP cores, including the high performance scalable RISC-V multiprocessor IP eVocore P8700, and enable customers to validate their end systems before silicon and accelerate software development.


Nvidia announced a large-memory AI supercomputer that uses NVLink interconnect technology with the NVLink Switch System to combine 256 of the company’s GH200 Grace Hopper superchips, allowing them to perform as a single GPU that it says provides 1 exaflop of performance and 144 terabytes of shared memory. Nvidia also debuted an accelerated networking platform designed to improve the performance and efficiency of Ethernet-based AI clouds. It combines the company’s Spectrum-4 Ethernet switch and the BlueField-3 DPU for predictable performance in multi-tenant environments along with acceleration software and SDKs for building cloud-native AI applications.

Intel updated its roadmap for high-performance computing and AI products, which includes CPUs to meet high memory bandwidth demands and AI-optimized GPUs with a modular, tile-based architecture.

Research notes

The University of Michigan launched a $55 million Quantum Research Institute to strengthen cross- disciplinary research collaborations among U-M faculty, government, and industry partners. QRI will operate a research incubator designed to provide faculty with services and resources, including seed funding and grant support.

The CHIPS Act, as well as the ongoing need for talent, is causing both industry and academia in America to rethink engineering education, resulting in new interdisciplinary approaches and stronger partnerships to get students hands-on experience.

As one example, Michigan launched a Semiconductor Talent Action Team that aims to build the state’s semiconductor workforce. It will develop semiconductor education curricula and flexible career training models, as well as create ways to engage pre-K-12 students in semiconductors. The program will also create a scholarship program.

IonQ, University of California Berkeley, and University of London researchers explored how to make quantum circuits model the process of human cognition. In particular, they looked at modeling how the relationship between concepts impacts other decisions, such as how one question being asked can have an impact on the answers to subsequent questions.

Researchers at Nanjing University, Southeast University, and Purple Mountain Laboratories propose a parallel in-memory wireless computing scheme capable of performing computations and wireless transmission concurrently on the same hardware. The design uses memristive crossbar arrays and takes advantage of the analog in-memory computing capabilities of memristors, enabling wireless signals to be processed in the path of data transmission in real time.

Researchers at the National Institute of Standards and Technology (NIST) fabricated a device to boost the conversion of heat into electricity. The fabrication technique involves depositing hundreds of thousands of microscopic columns of gallium nitride atop a silicon wafer. Layers of silicon are then removed from the underside of the wafer until only a thin sheet of the material remains. The interaction between the pillars and the silicon sheet slows the transport of heat in the silicon, enabling more of the heat to convert to electric current. The silicon sheets could be wrapped around steam or exhaust pipes to convert heat emissions into electricity that could power nearby devices or be delivered to a power grid. Another potential application would be cooling computer chips.

Read the latest power and performance tech papers.

Upcoming Events

  • RISC-V Summit Europe – June 5-9 (Barcelona, Spain)
  • Radio Frequency Integrated Circuits Symposium-RFIC 2023 – June 11-13 (San Diego, CA)
  • ISCA 2023: International Symposium on Computer Architecture – June 17-21 (Orlando, FL)
  • MIPI DevCon 2023: Mobile and Beyond – June 30 (San Jose, CA)
  • DAC 2023: Design Automation Conference – July 9-13 (San Francisco, CA)
  • 2023 Flash Memory Conference & Expo – August 8-10 (Santa Clara, CA)
  • DARPA: Electronics Resurgence Initiative (ERI) – August 22-24 (Seattle, WA)
  • Hot Chips 2023 – August 27-29 (Hybrid online & Stanford, CA)
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • Holistic Power Reduction
  • Making Tradeoffs With AI/ML/DL
  • Rethinking Engineering Education In The U.S.
  • Software-Defined Hardware Architectures
  • Chiplet Planning Kicks Into High Gear
  • Chip Design CEO Outlook
  • IP Becoming More Complex, More Costly

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