Week In Review: Design, Low Power

Tools & IP
OneSpin revealed its latest formal app, Connectivity XL, providing formal connectivity checking to 7nm, multi-billion gate SoC designs. The app generates detailed connectivity specification tables from abstract connectivity specs through a dedicated checking engine that integrates structural and formal analysis to perform on-the-fly, automated abstractions. It supports verification of direct, delayed, conditional and other connection types and enables verification of routing of global signals such as clock, reset and scan enable, I/O pads multiplexing and IP integration.

ANSYS unveiled the latest version of its simulation suite, ANSYS 2019 R1. It includes EMI Scanner, a feature to identify areas of potential electromagnetic interference on PCB designs prior to simulation. Other additions include electromigration analysis to predict mean time to failure for on-chip and advanced electronic packaging structures and a workflow to calculate the electromagnetic noise of a machine when it vibrates due to electromagnetic forces. The embedded software suite also simplifies compliance with industry standards like AUTOSAR and ISO 26262 when developing model-based systems and software for autonomous vehicles.

Rambus successfully taped out its GDDR6 PHY on TSMC’s 7nm FinFET process, which is now available for licensing. It provides speed of up to 16 Gbps for a maximum bandwidth of up to 512 Gbps. The IP is provided as a timing-closed hard macro solution. PCB and package design support is available. Hemant Dhulla, vice president and general manager of Rambus’ data center and communications business, said there were three major challenges to solve. One is that 7nm is the leading edge of design today, and much of the design work there is customized. Second, there were technical challenges in achieving 16Gbps speeds. And third, the PHY had to be developed at the same time the industry was developing GDDR6. He said one of the key applications will be AI chips.

Andes made its AndeSight IDE for software development for RISC-V based SoCs free to download. Based on Eclipse, the IDE features include a meta linker script editor, flash in-system-programming, virtual hosting, meta-file-based bit-field viewer for SoC registers, script-based RTOS awareness debugging, and break and display on exceptions.

The Bluetooth SIG released Bluetooth 5.1, which adds a new direction finding feature, Angle of Arrival (AoA) and Angle of Departure (AoD), for location services. According to the group, the feature “allows devices to determine the direction of a Bluetooth signal, thereby enabling the development of Bluetooth proximity solutions that can understand device direction as well as Bluetooth positioning systems that can achieve down to centimeter-level location accuracy.”

CEVA uncorked Bluetooth 5.1 IP, available in both Bluetooth Dual Mode and Bluetooth Low Energy, which includes the new feature.

eSilicon teamed up with Wild River Technology on an advanced test system for 56/112G PAM4 operation using the upcoming IEEE P370 standard. The design employed a channel-modeling platform to improve de-embedding quality out past 70GHz, establishing clear targets of equalization and creating an advanced reference design suited for immediate 3D electromagnetic design. The core of the design was Samtec’s Bulls Eye Test Point System; tools were also used from Keysight, ANSYS, and Simberian. The next phase is to design and build a test socket suited for 70GHz.

Numbers & People
Rambus reported fourth quarter financial results with revenue of $68.5 million. On a GAAP basis, the company saw a net loss per share of $0.02 for the quarter, with non-GAAP income per share of $0.09. This year, the company adopted new accounting standards; under the previous guidelines, Q4 2018 revenue was $102 million (up 0.1% from $101.9 million), GAAP income per share was $0.23 (up from a net loss of $0.33 per share in Q4 2017), and non-GAAP income was $0.28 (up 47.4% from $0.19 per share).

For the 2018 year, Rambus saw revenue of $231.2 million, with GAAP net loss per share of $1.46 and non-GAAP net loss per share of $0.06, using the new accounting standards. Under the previous guidelines, revenue was $401.1 million for the year (up 2% from $393.1 million in 2017) with GAAP net loss per share of $0.14 (up 33% from a net loss of $0.21 per share) and non-GAAP net income of $0.92 per share (up 35% from a net income of $0.68 per share last year). Rambus noted that it began shipping customer samples of DDR5 memory buffer chips at the top-end speeds for both the RCD and DB chips. Additionally, its high-speed IP cores business saw a CAGR of over 50% over the past four years.

Intel named Robert (Bob) Swan as the company’s new CEO. Swan has been serving as interim CEO for seven months since the departure of Brian Krzanich. Swan has also been serving as the company’s CFO, a position held since 2016. Todd Underwood, vice president of Finance and director of Intel’s Corporate Planning and Reporting, will assume the role of interim CFO. Prior to joining Intel, Swan served as an operating partner at General Atlantic LLC and served on Applied Materials’ board of directors, as well as nine years as eBay’s CFO.

Events
DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.