Week In Review: Design, Low Power

Tools
OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effects and also verifies that cores do not contain hardware Trojans or other unintended functionality.

UltraSoC announced its embedded analytics architecture fully supports Western Digital’s RISC-V SweRV Core and associated OmniXtend cache-coherent interconnect. The debug and on-chip analytics ecosystem will support the requirements of both Western Digital’s internal development teams and third parties choosing to adopt the SweRV Core for their own applications. SweRV is intended for development of open, purpose-built compute architectures for Big Data and Fast Data environments.

Breker Verification Systems added new development flows to its Trek5 verification tool suite. New capabilities allow tests to be optimized for UVM block verification, Software-Driven Verification (SDV) and Post-Silicon environments, in addition to Portable Stimulus model solving.

Concept Engineering’s RTLvision PRO tool for debugging, visualization, and analyzing waveforms will be integrated within Metrics’ cloud-based open platform ecosystem for verification. The tool provides detailed schematics of violated circuit paths, design hierarchy, clock and reset logic and allows for cross-probe from schematic to SystemVerilog source code.

IP
Arm debuted two new infrastructure-class platforms in its Neoverse family. The company says its N1 platform is optimized for 7nm process technology and provides +60% integer performance improvement and 2.5x more performance on key cloud workloads over the previous 16nm generation. It also claims a 30% power efficiency improvement over Cortex-A72 in the same process and includes server-class virtualization, RAS support, power and performance management, and system level profiling.

The E1 platform is designed to maximize throughput while balancing compute and efficiency requirements and provides 2.7x throughput performance with 2.4x throughput-to-power efficiency and 2.1x compute performance over the Cortex-A53. Applications include limited power deployments such as Power-over-Ethernet driven wireless access devices or low-power 5G edge transport nodes.

Cadence noted its tools and IP have been optimized to support the Arm Neoverse N1 platform, including a 7nm full-flow digital implementation and signoff Rapid Adoption Kit. The two companies also collaborated on the Neoverse N1 System Design Platform (SDP), based on the Neoverse N1 platform and Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP.

Rambus uncorked 32G Multi-protocol SerDes PHY on GlobalFoundries’ 22nm FD-SOI (22FDX) platform for high-volume, high-performance applications. The SerDes PHY delivers data rates up to 32 Gbps and supports multiple standards including PCIe 4.0, JESD204B/C, CPRI, and Ethernet. It is targeted at high-speed wireline, wireless 5G infrastructure and data center applications.

Synopsys and GlobalFoundries will team up to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare Foundation, Analog, and Interface IP for the GF 22nm FD-SOI (22FDX) process. The IPs, which includes Logic Libraries, Embedded Memories, Data Converters, LPDDR4, PCI Express 3.1, USB 2.0/3.1, and MIPI D-PHY IP, implement additional automotive-grade design rules for the 22FDX process to meet reliability and 15-year automotive operation requirements.

Dolphin Integration is working with GlobalFoundries to develop a series of off-the-shelf adaptive body bias (ABB) solutions for GF’s 22nm FD-SOI (22FDX) process technology. ABB uses forward and reverse body bias techniques to dynamically compensate for PVT variations and aging effects. The solutions in development will include self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening.

Standards
JEDEC published the LPDDR5 standard, JESD209-5. LPDDR5 will eventually operate at an I/O rate of 6400 MT/s, 50% higher than that of the first version of LPDDR4. LPDDR5 features a redesigned 16Banks programmable architecture and multi-clocking architecture. It introduces two new command-based operations to improve system power consumption by reducing data transmission: Data-Copy and Write-X. The Data-Copy command instructs the LPDDR5 device to copy data transmitted on a single I/O pin to the other I/O pins, eliminating the need to transmit data to the other pins. The Write-X command instructs the device to write all-ones or all-zeros to a specific address, eliminating the need to send data from the SoC to the LPDDR5 device. The standard also supports Link Error Correcting Code (ECC) on the interface between the SoC and DRAM.

Deals
Samsung Foundry’s industry-first gate-all-around (GAA) SoC test chip utilized Synopsys’ Fusion Design Platform, including place-and-route technology, for full-flow validation of target power, performance, and area. The companies emphasize that leading edge process scaling calls for greater collaboration between the EDA industry and the foundry.

Numbers
Cadence made a $150 million investment in Green Hills Software, acquiring a 16% ownership stake in the embedded safety and security software company. Green Hills’ EAL6+ certified INTEGRITY-178B real-time operating system is used in the aerospace/defense and automotive industries. The two companies will work on producing integrated hardware and software security solutions; Cadence CEO Lip-Bu Tan will join Green Hill’s board.

Synopsys reported first quarter 2019 financial results with revenue of $820.4, up 6.6% from Q1 last year. On a GAAP basis, income was $1.01 per share for the quarter, up from a loss of $0.02 per share in Q1 2018. Non-GAAP income was $1.08 per share, down 1.8% from $1.10. Synopsys began reporting its software integrity business separate from its EDA, IP, and semiconductor services products; at $82.5 million, software integrity made up 10% of the company’s revenue in Q1. The growth of AI-focused chips is a boon, noted CEO Aart de Geus, with the number of customers and designs growing: “Competition among AI-specific companies is fierce, and indeed for anyone incorporating AI into their chips, with an intense race to market and a broad set of competing architectures.”

Cadence reported fourth quarter 2018 financial results with revenue of $570 million, GAAP income per share of $0.35, and non-GAAP income per share of $0.52. The company adopted new accounting standards this year; under the previous rules, revenue for the quarter was $579 million, up 15.3% from Q4 2017. GAAP income per share was $0.36 in Q4 2018, compared to a net loss of $0.05 per share in Q4 2017. Non-GAAP income for the quarter was $0.51 per share, up 30.8% from $0.39 per share in the same quarter last year.

For the whole of 2018, Cadence saw revenue of $2.138 billion, GAAP net income of $1.23 per share, and non-GAAP net income of $1.87 per share. Under the previous rules, the year’s revenue was $2.146 billion, up 10.5% from 2017. GAAP income per share was $1.25, up 71.2% from $0.73 per share, while non-GAAP income in 2018 was $1.88 per share, up 34.3% from $1.40 per share. CEO Lip-Bu Tan cited aerospace and defense as a major vertical segment for the company and highlighted efforts to expand beyond EDA to the safety and security market. For the first quarter of 2019, the company expects total revenue in the range of $565 million to $575 million and expects $2.270 billion to $2.310 billion in revenue for 2019.

Events
DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.