What’s After 10nm?

Prior to 28nm the semiconductor road map was astoundingly predictable. Every two years you could be assured that features would shrink until there were no more atoms left.

Two big things and lots of little things later, the trajectory looks much more uncertain.

On the large things side are the obvious culprits—EUV delays, and RC delay caused by thinner wires. This is tough science. Problems are complex and progress is frustratingly slow, even with the best engineering teams from around the world working on these problems.

Problem No. 1. Had extreme ultraviolet lithography been ready when it was originally slated to hit the market, at 45nm or at least by 28nm, one major issue would have been resolved. There are legions of doubters about whether EUV will be ready even at 7nm—with readiness defined as an acceptable number of wafers per hour for a reasonable cost. At 7nm, it is likely that even EUV will require double patterning, and at 5nm it could require quadruple patterning (double double patterning), or triple patterning.

That sounds bad until you realize that 193nm immersion lithography will likely require octa-patterning by 5nm, with up to 8 different colors required. That’s why the industry is still rooting for EUV. There are only three primary colors, plus white and black, so the industry will be working with shades of colors by that point. Full-spectrum vision suddenly will become an important prerequisite for the job.

Problem No. 2. Wires don’t scale. They’re getting longer and thinner, and there is so much congestion around memories that what started out as just an RC delay problem—electrons not moving through wire quickly enough and generating heat along the way—is now splintering into a bundle of new problems. Signal integrity is the most obvious, but there are issues with premature circuit aging, thermal runaway, ESD, electromigration, and noise from both insufficient insulation and power.

There are all sorts of other issues, as well. Margining/guard-banding doesn’t work at advanced nodes, which is a problem for anyone designing a chip for multiple sockets. Guard-banding is useful for a number of reasons. For one thing, it speeds designs along to tapeout. For another, it simplifies the design process because it builds in safeguards in case something is overlooked, which in a complex SoC is very possible. And third, it adds flexibility into designs so they can be used for multiple sockets.

If a chip can’t be used in multiple places, it has to generate enough volume or be priced high enough to warrant the NRE investment in the first place. First-time silicon and correct-by-design are great concepts, but they’re much harder to achieve at new nodes for reasons ranging from process variability to tools that can only be optimized with time and experience. With compressed design schedules, time is under extreme pressure and experience is almost non-existent.

There are a few other pieces to this puzzle, as well. Packaging now needs to be considered as part of the overall design; dynamic power becomes more of a problem at each new node; and quantum effects begin adding uncertainty to the whole equation.

So do you go with finFETs to gate-all-around FETs or tunnel FETs, or is a planar solution with FD-SOI at 14nm good enough? Or how about a stacked die, which raises a different set of questions.

That all leads back to the question, what’s after 10nm? The obvious answer would be 7nm, but whether it’s the correct answer remains to be seen. There are lots of variables in play, from science to engineering to business. And right now, there are a lot of unanswered questions in all three of those areas. For the first time there is a lack of visibility in all of them about what’s next, which is especially daunting because they’re all interdependent. That makes it very difficult to define progress and predict where the semiconductor industry should place its next very expensive bets.