What’s After NAND Flash?

By Mark LaPedus
For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve.

Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And there is an increase in cell-to-cell interference in the word lines.

“The floating gate has been very successful in scaling down to the current 20nm node or even the 1xnm node,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “There is not much room for the floating gate to scale. Nobody really believes that planar NAND can go below 10nm.”

Today, the Toshiba-SanDisk duo is shipping NAND devices based on the world’s most advanced process, a 19nm technology. Going forward in NAND, Lee and others see at least two or more nodes remaining in the 1xnm regime.

The question is what’s after NAND flash? Currently, the industry is pursuing three basic categories in the NAND replacement sweepstakes: scaling existing NAND; 3D NAND; and the next-generation memory types.

There is no clear-cut winner right now. But in some circles, the initial and most promising successor is 3D NAND. “3D NAND is an extension of existing NAND,” Lee said. “Vertical NAND is in the development stage right now. The timeline for mass production is as early as 2013. Some companies have announced 2015.”

Defying the odds
Clearly, flash scaling has defied the odds. Ten years ago, Intel, the first vendor that commercialized NOR flash, predicted that flash would hit the wall at 65nm. Banking on those predictions, a number of firms began to develop various next-generation memory technologies that could replace NAND, NOR or DRAM—or all three. FeRAM, MRAM, phase-change and ReRAM are among those candidates.

The prediction was wrong, however. NAND has scaled down to 19nm, while NOR has migrated to 45nm. Thanks to 193nm immersion lithography and self-aligned double patterning (SADP), flash vendors have been able to scale the floating gate.

The ability to scale NAND and NOR has also pushed out the need for the next-generation memory types. And besides, most of these new memory types are still in R&D. They are expensive to make and difficult to scale.

Scaling today’s NAND down to 10nm is also difficult. NAND vendors may have to use self-aligned quadruple patterning, as extreme ultraviolet (EUV) lithography remains delayed. “NAND is even beyond current EUV resolutions. Even if EUV is available as of today, double patterning has to be used together with EUV,” Lee said.

There is also a remote chance that today’s 2D NAND could scale further using charge trap technology. Charge trap uses a silicon nitride film to store electrons. “I think the generation of charge trap flash as a planar device is limited,” he said.

Initially, if or when today’s NAND runs out of gas, the industry is banking on 3D NAND. “With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition,” Lee said.

3D NAND is also challenging, but the production steps are slightly different than 3D stacked DRAM and logic. The key step to 3D NAND is to build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers. Another key step is to fill the deep memory holes or trench slits. “The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask,” Lee said in a recent paper.

There’s another challenge as well: Can the 3D NAND developers put their products into production? The main 3D NAND contenders are Toshiba’s BiCS, Samsung’s VG-NAND, Macronix’ BE-SONOS, Hynix’ vertical cylindrical FG, SanDisk’s 3D memory and Intel/Micron’s stackable PCM, according to Forward Insights.

The 3D NAND industry emerged in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCs makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules.

In 2009, Samsung described its 3D NAND technology based on a terabit cell array transistor (TCAT). A year later, Macronix talked about a BE-SONOS charge-trapping technology. And Hynix is developing a 3D dual control-gate with a surrounding floating-gate.

One of the newer candidates is the stackable phase-change memory (PCM) device from Intel and Micron. Micron recently announced a 2D PCM device based on a 45nm process. In PCM, it is difficult to scale the cell array. PCM is also limited by the power required to change from the crystalline to an amorphous state.

Researchers are looking at new materials beyond traditional GST-225 schemes to overcome these limitations. Among those materials are binary and ternary alloys like germanium telluride (GeTe). “GeTe is one of the enablers,” said Jean-Luc Delcarri, general manager of Altatech, a CVD and inspection equipment subsidiary of Soitec. Altatech has installed its CVD system at CEA-Leti, which is developing PCM for the sub-20nm node.

It’s unclear which 3D NAND devices will eventually move into production, but there is a huge appetite for NAND in mobile and other applications. “I can’t say which vendor is ahead,” Applied’s Lee said. “I think vertical NAND will likely be adopted in traditional applications. The biggest applications are smartphones, tablets and mobile computing. What is still to come are SSDs.”

3D NAND debate
Analysts have slightly different viewpoints. “The only company that has told me a schedule is Toshiba, who plans to sample 3D NAND in 2013,” said Jim Handy, an analyst with Objective-Analysis, a research firm.

“The thing that is driving (3D NAND) is the use for more bytes in video,” Handy said. “3D NAND is straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM and trenches like a trench cell DRAM. I have heard that the aspect ratios for the trenches are somewhat tricky.”

Greg Wong, an analyst with Forward Insights, does not see commercial production for 3D NAND until 2015 or so. “NAND flash manufacturers are pushing planar NAND flash to sub-20nm nodes. As they extend the roadmap for 2D NAND, the introduction of 3D NAND gets pushed out,” Wong said.

“There are technical challenges with etching a high aspect ratio pillar and multiple stacks, but the big challenge is economic. The investment required is significantly more for 3D than 2D NAND,” Wong said. “3D NAND employing charge trapping technology will have some challenges in meeting the performance specifications of 2D NAND. However, by stacking multiple layers, lower cost per bit can be attained.”

Alan Niebel, president of Web-Feet Research, agreed. “3D NAND should enter the market around 2015 (or after). Designing and qualifying 3D NAND will probably be a seven year process, which started in 2007. Concurrently, it takes easily another five years to perfect the manufacturing and especially in manufacturing 3D ICs,” Niebel said.

“3D NAND should have a much higher areal density and lower cost than 2D NAND, since the F2 divides in half with each layer, probably four layers max per chip. Performance in both speeds (read and write) and endurance will deteriorate with 3D NAND compared to 2D,” he added. “The stacked structure will have more bits to address, more interconnects with each layer and longer distance from cell to controller that will add latency to the 3D. Perhaps endurance may not suffer too much if the lithography is the same for 2D and 3D NAND cells, but by stacking them in 3D, these additional steps could possibly fatigue the control gate oxides and further reduce endurance.”

Besides the technology challenges, Applied’s Lee sees another hurdle—cost. “NAND vendors will go into 3D only if they can meet a cost target. We are quite confident the cost structure of 3D NAND will be lower than 2D NAND. The reason is that 3D NAND is less lithographic and double-patterning heavy,” he said.